Patents by Inventor Markus Broell

Markus Broell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210104645
    Abstract: A method for producing a contact structure for an optoelectronic semiconductor component is given, comprising the steps: a) providing a growth substrate having a semiconductor body which is grown thereon and comprises a first and a second region, and an active region, b) creating at least one first recess which, starting from the second region, extends completely through the active region into the first region and does not completely penetrate the first region, c) inserting a first electrically conductive contact material into the first recess, d) fixing the semiconductor body with the side facing away from the growth substrate on a support substrate, and detaching the growth substrate from the semiconductor body, e) creating at least one second recess extending from the first region to the first recess so that the first recess and the second recess form a feedthrough through the semiconductor body, f) introducing a second electrically conductive contact material into the second recess in such a way that t
    Type: Application
    Filed: July 4, 2018
    Publication date: April 8, 2021
    Inventors: Wolfgang SCHMID, Markus BRÖLL
  • Publication number: 20210050484
    Abstract: An optoelectronic semiconductor component and a method for producing an optoelectronic semiconductor component are disclosed. In an embodiment an optoelectronic semiconductor component includes a semiconductor layer sequence having a first region of a first conductivity type, a reflection layer, a passivation layer arranged between the semiconductor layer sequence and the reflection layer, a first barrier layer arranged between the first region of the semiconductor layer sequence and the passivation layer and a second barrier layer arranged between the passivation layer and the reflection layer, wherein the first barrier layer is configured to reduce or prevent diffusion of contaminants from the passivation layer into the semiconductor layer sequence, and wherein the second barrier layer is configured to reduce or prevent diffusion of contaminants from the passivation layer into the reflection layer.
    Type: Application
    Filed: January 24, 2019
    Publication date: February 18, 2021
    Inventors: Brendan Holland, Markus Bröll
  • Publication number: 20200388988
    Abstract: A method of producing laser bars or semiconductor lasers includes providing a carrier composite to form a plurality of carriers for the laser bars or for the semiconductor lasers, providing a semiconductor body composite including a common substrate and a common semiconductor layer sequence grown thereon, forming a plurality of separation trenches through the common semiconductor layer sequence such that the semiconductor body composite is divided into a plurality of semiconductor bodies, applying the semiconductor body composite to the carrier composite such that the separation trenches face the carrier composite, thinning or removing the common substrate, and singulating the carrier composite into a plurality of carriers, wherein a plurality of semiconductor bodies are arranged on one of the carriers, and the semiconductor bodies arranged on one common carrier are laterally spaced apart from one another by the separation trenches.
    Type: Application
    Filed: April 16, 2018
    Publication date: December 10, 2020
    Inventors: Roland Heinrich Enzmann, Hubert Halbritter, Markus Bröll
  • Publication number: 20200313036
    Abstract: Disclosed herein are methods, systems, and apparatuses for an light emitting diode (LED) array apparatus. In some embodiments, the LED array apparatus may include a plurality of mesas etched from a layered epitaxial structure. The layered epitaxial structure may include a P-type doped semiconductor layer, a active layer, and an N-type doped semiconductor layer. The LED array apparatus may also include one or more regrowth semiconductor layers, including a first regrowth semiconductor layer, which may be grown epitaxially over etched facets of the plurality of mesas. In some cases, for each mesa, the first regrowth semiconductor layer may overlay etched facets of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer, around an entire perimeter of the mesa.
    Type: Application
    Filed: March 29, 2020
    Publication date: October 1, 2020
    Inventors: Markus BROELL, Michael GRUNDMANN, David HWANG, Stephan LUTGEN, Brian Matthew MCSKIMMING, Anurag TYAGI
  • Publication number: 20190386174
    Abstract: An optoelectronic semiconductor chip including a semiconductor layer sequence containing a phosphide compound semiconductor material, wherein the semiconductor layer sequence includes a p-type semiconductor region, an n-type semiconductor region and an active layer disposed between the p-type semiconductor region and the n-type semiconductor region, a current spreading layer including a transparent conductive oxide adjoining the p-type semiconductor region, and a metallic p-connection layer at least regionally adjoining the current spreading layer, wherein the p-type semiconductor region includes a p-contact layer adjoining the current spreading layer, the p-contact layer contains GaP doped with C, a C dopant concentration in the p-contact layer is at least 5*1019 cm?3, and the p-contact layer is less than 100 nm thick.
    Type: Application
    Filed: January 23, 2018
    Publication date: December 19, 2019
    Inventors: Xue Wang, Markus Broell
  • Publication number: 20190386175
    Abstract: A radiation-emitting semiconductor body having a semiconductor layer sequence includes an active region that generates radiation, an n-conducting region and a p-conducting region, wherein the active region is located between the n-conducting region and the p-conducting region, the p-conducting region includes a current expansion layer based on a phosphide compound semiconductor material, and the current expansion layer is doped with a first dopant incorporated at phosphorus lattice sites.
    Type: Application
    Filed: March 5, 2018
    Publication date: December 19, 2019
    Inventors: Xue Wang, Markus Bröll, Anna Nirschi
  • Publication number: 20190371966
    Abstract: An optoelectronic semiconductor chip includes a p-type semiconductor region, an n-type semiconductor region, an active layer disposed between the p-type semiconductor region and the n-type semiconductor region and formed as a multiple quantum well structure and having alternating quantum well layers and barrier layers, the quantum well layers emitting a first radiation in a first wavelength range, and at least one further quantum well layer disposed outside the multiple quantum well structure that emits a second radiation in a second wavelength range, wherein the first wavelength range is in an infrared spectral range invisible to a human eye, and the second wavelength range includes wavelengths at least partially visible to the human eye.
    Type: Application
    Filed: February 22, 2018
    Publication date: December 5, 2019
    Inventors: Andreas Rudolph, Markus Broell, Wolfgang Schmid, Johannes Baur, Martin Rudolf Behringer
  • Patent number: 10347792
    Abstract: An optoelectronic component is disclosed. In an embodiment the component includes a semiconductor layer sequence with a first layer, a second layer and an active layer arranged between the first and second layer, wherein the active layer directly borders the first and second layer, a radiation surface directly bordering the second layer, one or more contact isles for electrically contacting the first layer and one or more through-connections for electrically contacting of the second layer, wherein the through-connections are formed through the first layer and the active layer and open into the second layer, wherein the contact isles are located laterally next to one another directly on a rear side of the first layer facing away from the radiation surface, wherein the through-connections are arranged in regions between the contact isles in a top view of the rear side.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: July 9, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Philipp Kreuter, Tansen Varghese, Wolfgang Schmid, Markus Bröll
  • Publication number: 20190131495
    Abstract: An optoelectronic component is disclosed. In an embodiment the component includes a semiconductor layer sequence with a first layer, a second layer and an active layer arranged between the first and second layer, wherein the active layer directly borders the first and second layer, a radiation surface directly bordering the second layer, one or more contact isles for electrically contacting the first layer and one or more through-connections for electrically contacting of the second layer, wherein the through-connections are formed through the first layer and the active layer and open into the second layer, wherein the contact isles are located laterally next to one another directly on a rear side of the first layer facing away from the radiation surface, wherein the through-connections are arranged in regions between the contact isles in a top view of the rear side.
    Type: Application
    Filed: July 7, 2016
    Publication date: May 2, 2019
    Inventors: Philipp Kreuter, Tansen Varghese, Wolfgang Schmid, Markus Bröll
  • Patent number: 10263143
    Abstract: A semiconductor chip (20) is described comprising a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material wherein the semiconductor layer sequence (10) contains a p-type semiconductor region (4) and an n-type semiconductor region (2). The n-type semiconductor region (2) comprises a superlattice structure (20) for improving current spreading, wherein the superlattice structure (20) has a periodic array of semiconductor layers (21, 22, 23, 24). A period of the superlattice structure (20) has at least one undoped first semiconductor layer (21) and a doped second semiconductor layer (22), wherein an electronic band gap E2 of the doped second semiconductor layer (22) is larger than an electronic band gap E1 of the undoped first semiconductor layer (21).
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 16, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Xue Wang, Markus Broell, Stefan Barthel
  • Patent number: 10181547
    Abstract: An optoelectronic semiconductor chip (1) is provided which has a semiconductor body comprising a semiconductor layer sequence (2) with an active region (20) provided for generating and/or receiving radiation, a first semiconductor region (21) of a first conduction type, a second semiconductor region (22) of a second conduction type and a cover layer (25). The active region (20) is arranged between the first semiconductor region (21) and the second semiconductor region (22) and comprises a contact layer (210) on the side remote from the active region. The cover layer (25) is arranged on the side of the first semiconductor region (21) remote from the active region (20) and comprises at least one cut-out (27), in which the contact layer (210) adjoins the first connection layer (3). The cover layer is of the second conduction type. Furthermore, a method is provided for producing optoelectronic semiconductor chips.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: January 15, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Petrus Sundgren, Markus Broell
  • Publication number: 20180301595
    Abstract: A semiconductor chip (20) is described comprising a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material wherein the semiconductor layer sequence (10) contains a p-type semiconductor region (4) and an n-type semiconductor region (2). The n-type semiconductor region (2) comprises a superlattice structure (20) for improving current spreading, wherein the superlattice structure (20) has a periodic array of semiconductor layers (21, 22, 23, 24). A period of the superlattice structure (20) has at least one undoped first semiconductor layer (21) and a doped second semiconductor layer (22), wherein an electronic band gap E2 of the doped second semiconductor layer (22) is larger than an electronic band gap E1 of the undoped first semiconductor layer (21).
    Type: Application
    Filed: April 9, 2018
    Publication date: October 18, 2018
    Inventors: Xue WANG, Markus BROELL, Stefan BARTHEL
  • Publication number: 20180212107
    Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment, the chip includes a semiconductor layer sequence with a first side, a second side and an active zone and at least one via electrically contacting the first side with the second side through the active zone, wherein the via has a base region including a cylinder, a truncated cone or a truncated pyramid, wherein the via is surrounded in a lateral direction by an electric insulation layer, wherein the via has a contact region including a truncated cone, a truncated pyramid, or a spherical or aspherical body, wherein the contract region directly follows the base region, wherein the contact region is in direct contact with the second side, wherein a first flank angle of the base region is different from a second flank angle of the contact region, and wherein the first and second flank angles are related to the lateral direction.
    Type: Application
    Filed: July 7, 2016
    Publication date: July 26, 2018
    Applicants: OSRAM Opto Semiconductors GmbH, OSRAM Opto Semiconductors GmbH
    Inventors: Philipp Kreuter, Markus Bröll, Jens Müller
  • Patent number: 10026871
    Abstract: An optoelectronic device is disclosed. In an embodiment the device includes a semiconductor crystal with a surface having a first lateral region, a second lateral region and a third lateral region, a contact area arranged on the surface in the first lateral region, the contact area comprising a first metal and a first layer including a dielectric arranged on the surface in the third lateral region. The device further includes a second layer having an optically transparent, electrically conductive material arranged on the contact area, the first layer and the second lateral region of the surface and a third layer having a second metal arranged on the second layer.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: July 17, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Markus Bröll, Christoph Klemp, Wolfgang Schmid
  • Publication number: 20180151777
    Abstract: An optoelectronic device is disclosed. In an embodiment the device includes a semiconductor crystal with a surface having a first lateral region, a second lateral region and a third lateral region, a contact area arranged on the surface in the first lateral region, the contact area comprising a first metal and a first layer including a dielectric arranged on the surface in the third lateral region. The device further includes a second layer having an optically transparent, electrically conductive material arranged on the contact area, the first layer and the second lateral region of the surface and a third layer having a second metal arranged on the second layer.
    Type: Application
    Filed: January 24, 2018
    Publication date: May 31, 2018
    Inventors: Markus Bröll, Christoph Klemp, Wolfgang Schmid
  • Patent number: 9882090
    Abstract: A method for producing an optoelectronic component is disclosed. A first layer which has a dielectric to the surface of a semiconductor crystal. A photoresist layer is applied and structured on the first layer. The photoresist layer is structured in such a way that the photoresist layer has an opening, The first layer is partially separated in order to expose a lateral region of the surface. A contact area having a first metal is applied in the lateral region of the surface. The photoresist layer is removed. A second layer, which comprises an optically transparent, electrically conductive material, and a third layer, which comprises a second metal, are applied.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: January 30, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Markus Bröll, Christoph Klemp, Wolfgang Schmid
  • Patent number: 9799801
    Abstract: A method for producing an optoelectronic semiconductor chip comprises the following steps: providing a substrate, depositing a sacrificial layer, depositing a functional semiconductor layer sequence, laterally patterning the functional semiconductor layer sequence, and oxidizing the sacrificial layer in a wet thermal oxidation process.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: October 24, 2017
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Christian Schmid, Julia Grosser, Richard Floeter, Markus Broell
  • Patent number: 9466764
    Abstract: The invention relates to an optoelectronic component (101, 301, 501), comprising a substrate (103, 303, 503), on which a semiconductor layer sequence (105, 305, 505) has been placed, wherein the semiconductor layer sequence (105, 305, 505) has at least one identifier (115, 315) for identifying the component (101, 301, 501). The invention also relates to a method for producing an optoelectronic component (101, 301, 501).
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 11, 2016
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Martin Rudolf Behringer, Christoph Klemp, Markus Broell
  • Publication number: 20160276534
    Abstract: An optoelectronic semiconductor chip (1) is provided which has a semiconductor body comprising a semiconductor layer sequence (2) with an active region (20) provided for generating and/or receiving radiation, a first semiconductor region (21) of a first conduction type, a second semiconductor region (22) of a second conduction type and a cover layer (25). The active region (20) is arranged between the first semiconductor region (21) and the second semiconductor region (22) and comprises a contact layer (210) on the side remote from the active region. The cover layer (25) is arranged on the side of the first semiconductor region (21) remote from the active region (20) and comprises at least one cut-out (27), in which the contact layer (210) adjoins the first connection layer (3). The cover layer is of the second conduction type. Furthermore, a method is provided for producing optoelectronic semiconductor chips.
    Type: Application
    Filed: November 4, 2013
    Publication date: September 22, 2016
    Applicant: Osram Opto Semiconductors GMBH
    Inventors: Petrus SUNDGREN, Markus BROELL
  • Publication number: 20160104819
    Abstract: A method for producing an optoelectronic semiconductor chip comprises the following steps: providing a substrate, depositing a sacrificial layer, depositing a functional semiconductor layer sequence, laterally patterning the functional semiconductor layer sequence, and oxidizing the sacrificial layer in a wet thermal oxidation process.
    Type: Application
    Filed: May 14, 2014
    Publication date: April 14, 2016
    Applicant: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Christian SCHMID, Julia GROSSER, Richard FLOETER, Markus BROELL