Abstract: A quantum computing system having a central controller with improved latency executes a first instruction at a processing unit of the central controller. The central controller interconnects a plurality of control entities for configuring and measuring a plurality of qubits. A set of selected channels carry measurement results for a first quantum computation by the plurality of qubits. When the first instruction is a multi-channel-receive instruction, the system stalls the processing unit from executing any further instructions until each channel of the set of two or more selected channels has provided an input from a remote peer. Different channels in the set of selected channels are examined simultaneously. The system resumes execution at the processing unit of a second instruction after the stalling.

Abstract: A quantum computing system that supports efficient multitasking receives messages from a classical computing system to a pool of qubits. Each received message is associated with a partition identifier. The system configures a first set of qubits in the pool of qubits to perform a first computing task based on received messages that are associated with a first partition identifier and a second set of qubits in the pool of qubits to perform a second computing task based on received messages that are associated with a second partition identifier. The system acquires a first set of measurements from the first set of qubits and a second set of measurements from the second set of qubits. The system relays the first and second sets of measurements to the classical computing system.

Abstract: Aspects of the disclosure relate to a processor core including an execution unit and a usage ratio controller. The execution unit is operable for executing a command forwarded to the execution unit. The usage ratio controller is operatively coupled with the execution unit. The usage ratio controller is operable for controlling a usage ratio of the execution unit. The usage ratio corresponds to the fraction of an observation time during which the execution unit is executing commands of an application. Other aspects of the disclosure relate to a method for detecting or analyzing a bottleneck in a processor core for a given application. The method includes controlling a usage ratio of at least one execution unit of the processor core and measuring the resulting application performance.

Abstract: Aspects of the disclosure relate to a processor core including an execution unit and a usage ratio controller. The execution unit is operable for executing a command forwarded to the execution unit. The usage ratio controller is operatively coupled with the execution unit. The usage ratio controller is operable for controlling a usage ratio of the execution unit. The usage ratio corresponds to the fraction of an observation time during which the execution unit is executing commands of an application. Other aspects of the disclosure relate to a method for detecting or analyzing a bottleneck in a processor core for a given application. The method includes controlling a usage ratio of at least one execution unit of the processor core and measuring the resulting application performance.

Abstract: A buffer is configured to store a plurality of last addresses accessed by a processor core from a memory. A minimum distance extraction circuit determines distances of a current memory address accessed by the processor core from each of the plurality of last addresses in the buffer and determines a minimum distance from the distances. A limit determination circuit compares the minimum distance to each of a plurality of ranges of distances and selects a range of the plurality of ranges within which the minimum distance falls. Each of a plurality of counters of a counter circuit is associated with a corresponding one of the plurality of ranges. A counter of the plurality of counters is to be incremented corresponding to the selected range.

Abstract: A buffer is configured to store a plurality of last addresses accessed by a processor core from a memory. A minimum distance extraction circuit determines distances of a current memory address accessed by the processor core from each of the plurality of last addresses in the buffer and determines a minimum distance from the distances. A limit determination circuit compares the minimum distance to each of a plurality of ranges of distances and selects a range of the plurality of ranges within which the minimum distance falls. Each of a plurality of counters of a counter circuit is associated with a corresponding one of the plurality of ranges. A counter of the plurality of counters is to be incremented corresponding to the selected range.

Abstract: A method, computer program product, and system for rerouting wires based on wire size and spacing requirements including partitioning a chip into a plurality of global routing tiles, assigning a set of wires to one or more of the plurality of global routing tiles, sorting the set of wires into one or more groups based on line spacing requirements for wires of the set of wires, each of the one or more groups includes one or more wires with a common line spacing requirement, and organizing the one or more groups in a numeric order based on the common line spacing requirement of each group.

Abstract: A method, computer program product, and system for rerouting wires based on wire size and spacing requirements including partitioning a chip into a plurality of global routing tiles, assigning a set of wires to one or more of the plurality of global routing tiles, sorting the set of wires into one or more groups based on line spacing requirements for wires of the set of wires, each of the one or more groups includes one or more wires with a common line spacing requirement, and organizing the one or more groups in a numeric order based on the common line spacing requirement of each group.

Abstract: A method for implementing a hardware design that includes using a computer for receiving structured data that includes a representation of a basic hardware structure and a complex hardware structure that includes the basic hardware structure, parsing the structured data and generating, based on a result of the parsing, commands of a hardware design environment.

Abstract: Calculating a timing delay in a repeater network in an electronic circuit. The repeater network comprises a plurality of driving cells. At least one loop comprising one or more pins and one or more driving cells for driving the loop is implemented. Each driving cell in the loop is arranged between two branches of the loop. For each driving cell, the loop is opened a plurality of times per driving cell, with one open at a time. A dedicated arrival time of a signal at each sink of the repeater network for the one open at a time per driving cell is calculated. The dedicated arrival time is stored. The calculation step and the storing step is repeated until the dedicated arrival time at each sink of the repeater network is available for each of the opens per driving cell.

Abstract: A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

Abstract: A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

Abstract: A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.

Abstract: The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

Abstract: A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value.

Abstract: A radiometric measuring arrangement for measuring fill level of a fill substance in a container includes: arranged one above the other in measurement operation on a first side of the container, two or more radiometric radiators, which, in measurement operation, send radioactive radiation through the container, and which, in measurement operation, are arranged in a measuring position in the interior of the container in a pressure resistant, protective tube protruding laterally into the container; and, arranged on a second side of the container lying opposite to the radiators, at least one detector, which serves to receive radiation intensity penetrating through the container as a function of fill level and to convert such into a fill level dependent, electrical signal. The measuring arrangement permits achievement of a highly linear dependence of total detected radiation intensity on fill level.

Abstract: A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value.

Abstract: A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function to be solved by the electronic circuit. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

Abstract: A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

Abstract: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.