Patents by Inventor Markus Dankerl

Markus Dankerl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11158707
    Abstract: A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hanno Melzner, Markus Dankerl, Peter Irsigler, Sebastian Schmidt, Hans-Joachim Schulze
  • Publication number: 20210118992
    Abstract: A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.
    Type: Application
    Filed: September 2, 2020
    Publication date: April 22, 2021
    Inventors: Hanno Melzner, Markus Dankerl, Peter Irsigler, Sebastian Schmidt, Hans-Joachim Schulze