Abstract: A device (1) for generating a random bit sequence has a digital ring oscillator circuit (2) having at least one first feedback path (R8) and one second feedback path (R14). To this end, a changeover is performed between the feedback paths (R8, R14) at times which can be predetermined, and a random signal (OS) having a random level history can be tapped at an output node (4) of the ring oscillator circuit (2).

Abstract: An apparatus for generating a random bit sequence has a ring oscillator which includes inverting digital devices and on which an oscillator signal can be tapped. An intermediate storage element monitors and stores fluctuating levels of the oscillator signal. At least two controllable switch devices for simultaneously exciting at least two harmonic wave edges of the ring oscillator are provided in a signal path of the ring oscillator. The phasing of the two harmonic wave edges and a potential convergence thereof are subject to statistical fluctuations, which are used as a basis for the random bit generation. A corresponding random number generator can be used in particular as an FPGA for security applications, such as cryptographic methods. The apparatus has substantially digital components, which are easy to produce in a standardized manner. A dedicated regulating circuit is not necessary. The apparatus is also robust toward exterior influences.

Abstract: A random source for generating a random number r with a bit length k, r=r0, . . . , rk-1, a memory for storing a threshold value state variable s, which is represented by a number with a bit length n?k, s=s0, . . . , sn-1, and a comparator to compare two numbers with a bit length k, i.e. from r with a subset of the bits from s are provided. Two calculation rules R1 and R2, which are able to change the content of the memory for the threshold value state variable s (i.e. functions from s to s), are defined for a method of generating random wait states.

Abstract: A method and system for accelerated decryption of a cryptographically protected user data unit, wherein a transmitter initially generates a cryptographic key that is provided with a related key identification. The transmitter then performs asymmetrical encryption of the generated cryptographic key using a public cryptographic key and encryption of at least one user data unit using the generated cryptographic key. The encrypted user data unit, the asymmetrically encrypted cryptographic key and the related key identification of the cryptographic key are transported to a receiver that decrypts the received asymmetrically encrypted key using a private key, if verification of the received related key identification of the cryptographic key indicates the cryptographic key is not present in a decrypted state in the receiver. The receiver then decrypts the received cryptographically encrypted user data unit using the cryptographic key in the receiver or with the cryptographic key decrypted using the private key.

Abstract: A method and a system for naming-conflict-free integration of software components originating from software component manufacturers (OEM), comprising software development devices from different software component manufacturers (OEM) that manufacture and encrypt software components with the respective cryptographic key, wherein when a naming conflict occurs during the integration of encrypted software components, at least one of the encrypted software components in which the naming conflict occurred is expanded by a naming conflict resolution rule to thereby allows for the resolution of naming conflicts in encrypted software components that can originate from different software component manufacturers without the source code of the software components becoming visible to third parties.

Abstract: A method and system for confidentially providing a software component which is encrypted using a secret cryptographic key of a software component manufacturer, and the key is then encrypted using a first cryptographic system key, wherein the encrypted software component and the encrypted key are transported by the software component manufacturer to a destination system device. After decrypting the transported encrypted key using a second cryptographic system key, the transported encrypted software component is decrypted using the decrypted key, wherein the decrypted software component is provided for execution on the destination system device. The method can be used to protect source codes or object codes of a developed software component from access by a third party and still allows for processing using standard tools.

Abstract: An apparatus for generating a random bit sequence has a ring oscillator which includes inverting digital devices and on which an oscillator signal can be tapped. An intermediate storage element monitors and stores fluctuating levels of the oscillator signal. At least two controllable switch devices for simultaneously exciting at least two harmonic wave edges of the ring oscillator are provided in a signal path of the ring oscillator. The phasing of the two harmonic wave edges and a potential convergence thereof are subject to statistical fluctuations, which are used as a basis for the random bit generation. A corresponding random number generator can be used in particular as an FPGA for security applications, such as cryptographic methods. The apparatus has substantially digital components, which are easy to produce in a standardized manner. A dedicated regulating circuit is not necessary. The apparatus is also robust toward exterior influences.

Abstract: The invention relates to an encoding method for identifying a subsequential manipulation of a counter meter reading consisting, when the counter reading is increased or decreased, in activating the computation of a new encoded meter reading and in calculating a new encoded meter reading by applying a forward chain one-way function to the encoded meter reading, wherein a complex variable domain of said forward chain one-way function is included into the antecedent domain thereof.

Abstract: A device (1) for generating a random bit sequence has a digital ring oscillator circuit (2) having at least one first feedback path (R8) and one second feedback path (R14). To this end, a changeover is performed between the feedback paths (R8, R14) at times which can be predetermined, and a random signal (OS) having a random level history can be tapped at an output node (4) of the ring oscillator circuit (2).

Abstract: Random numbers can be generated in a statistically independent manner and with identical probability if the bits generated by a controlled bit generator are stored by a storage in a plurality of memory regions, wherein the bits are each stored in such memory regions associated with a difference of the bits of the values 1 and 0 generated up to the time of storage, and if all the bits stored within a memory region are subjected to algorithmic post-processing as soon as a predetermined number of bits within a memory region is exceeded. The fact that the bits are not stored and processed sequentially, i.e. in the order of generation, allows using a sequence of bits within which the individual bits are statistically independent of one another for the algorithmic post-processing. Thus, a way of performing algorithmic post-processing of the bits without reducing the entropy is provided.

Abstract: A device generates a random bit sequence with a digital ring oscillator circuit comprising logic components. The circuit has an input node and an output node, wherein the digital ring oscillator circuit is designed such that oscillation occurs during a change of state of a logic start signal coupled on the input node, said oscillation having a fixed point, and wherein on the output node a random signal can be tapped having an arbitrary level curve.

Abstract: Random numbers can be generated in a statistically independent manner and with identical probability if the bits generated by a controlled bit generator are stored by a storage in a plurality of memory regions, wherein the bits are each stored in such memory regions associated with a difference of the bits of the values 1 and 0 generated up to the time of storage, and if all the bits stored within a memory region are subjected to algorithmic post-processing as soon as a predetermined number of bits within a memory region is exceeded. The fact that the bits are not stored and processed sequentially, i.e. in the order of generation, allows using a sequence of bits within which the individual bits are statistically independent of one another for the algorithmic post-processing. Thus, a way of performing algorithmic post-processing of the bits without reducing the entropy is provided.

Abstract: A random number generator includes a noise signal generating device for supplying a noise signal, a sampling device connected between an output of the noise signal generating device and an output of the random number generator and sampling the noise signal in a sampling state and not sampling the noise signal in an idle state. The random number generator further includes a control oscillator for supplying a control alternating signal, the frequency of the control alternating signal of the control oscillator not being rigidly coupled to the frequency of the noise signal. The random number generator further includes an enabling device which puts the sampling device in the sampling state when the noise signal or the signal derived from the noise signal is in a first trigger state, and when, subsequently, the control alternating signal of the control oscillator is in a second trigger state.

Abstract: A random number generator includes a noise signal generating device for supplying a noise signal, a sampling device connected between an output of the noise signal generating device and an output of the random number generator and sampling the noise signal in a sampling state and not sampling the noise signal in an idle state. The random number generator further includes a control oscillator for supplying a control alternating signal, the frequency of the control alternating signal of the control oscillator not being rigidly coupled to the frequency of the noise signal. The random number generator further includes an enabling device which puts the sampling device in the sampling state when the noise signal or the signal derived from the noise signal is in a first trigger state, and when, subsequently, the control alternating signal of the control oscillator is in a second trigger state.

Abstract: A method for protecting an item of software, wherein at least one challenge means is associated with said protected item of software, and at least one response means accesses one private keying material. The challenge means has no access to said private keying material. The response means proves to the challenge means that the response means has access to the private keying material using an asymmetric probabilistic proof, e.g., zero knowledge proof. The challenge means validates this proof using the public keying material that corresponds to the response means' private keying material.

Abstract: A method for protecting an item of software, wherein at least one challenge is associated with the protected item of software, and at least one response accesses one private keying material. The challenge has no access to the private keying material. The challenge and the response are generating shared secret information, respectively, in accordance with an asymmetric confidentiality scheme. The response proves that it discovered the shared secret and the challenge validates the proof. The challenge proof validation procedure uses the public keying material that corresponds to the response private keying material.