Abstract: In an integrated-circuit chip having intercommunicating modular functional units of electrical circuits, wired transmission of sensitive information signals between the functional units of the electrical circuits involves generating a reference signal and coding the sensitive information signals, after being emitted by a generating functional unit in the chip, with the reference signal to disguise the sensitive information represented by the sensitive information signals. The coded sensitive information signals are decoded with the reference signal before the sensitive information signals are received by a processing functional unit in the chip. At least one signal of the reference signal and the decoded sensitive information signals are monitored, and a hacker attack is identified in response to a determination that the decoded sensitive information signal is other than a plausible signal.

Abstract: An electronic memory component provides a plurality of access-secured sub-areas. Each access-secured memory sub-area has at least one assigned parameter, for example, an address. The memory encrypts the assigned parameters of the access-secured sub-areas in such a way that on the one hand the security of such devices is increased considerably and on the other hand the associated expense and technical complexity are not too great. The encryption allows access to at least one sub-area dependent on at least one further sub-area.

Abstract: The invention relates to a method and an arrangement for increasing the security of circuits against unauthorized access, both of which can be used in particular to improve the security of cards, and particularly smart cards, against attacks in which the differential power analysis approach (DPA) is followed. DPA is a procedure that makes it possible to obtain not only purely functional details but also internal information stored in integrated circuits (e.g. smart-card controllers). The majority of non-clocked classes of circuit have the property that the performance of the circuit adjusts automatically to the voltage available. The invention adopts a new approach to enable integrated circuits and particularly non-clocked handshake logic to be protected against DPA. Advantage is taken in this case of a special property of self-timed logic by using a special power supply.

Abstract: The invention relates to a method and multiplier for multiplying two factors from the Galois field GF (2m*p), where each of the factors can be represented as a vector of p sub-blocks with a width of m bits and p, m are positive integers greater than 1. The method and multiplier allow for a polynomial multiplication to be performed quickly and efficiently with minimum requirements in respect of for storage space. Therefore, savings can thus be achieved in respect of power consumption, crystal surface and calculation time.

Abstract: A digital microelectronic circuit comprises a clocked data-processing unit (1) and a converting unit (2) which reads in data present at the output of the data-processing unit, performs a predetermined converting operation on the data and passes on the converted data. The converting unit is realized in an asynchronous logic circuit, such that the period of time for performing the converting operation is shorter than the shortest time interval to the next change of the data present at the output of the data-processing unit. In this way, fast, serial synchronous processes can be parallelized from the point of view of the slow synchronous system in synchronous systems which are slow relative thereto by using asynchronous logics, without a further high-frequency clock system being required.

Abstract: In order to further develop a data processing device, in particular an electronic memory component, comprising a plurality of access-secured sub-areas, in particular a plurality of access-secured memory areas, each having at least one assigned parameter (an, an?1, . . . , a0), in particular address, and a method of encrypting at least one parameter (an, an?1, . . . , a0 ) in particular the address, of at least one access-secured sub-area, in particular at least one access-secured memory area, of at least one data processing device, in particular at least one electronic memory component, in such a way that on the one hand the security of such devices is increased considerably and on the other hand the associated expense and technical complexity are not too great, it is proposed that the parameter (an, an?1, . . . , a0) of at least one sub-area be capable of encryption only in certain areas, i.e. in dependence on least one further sub-area (a?n, a?n?1, . . . , a?1, a?0).

Abstract: A data carrier that communicates confidential data is configured to mask process-dependent power consumption by using power stored in an internal capacitor. The capacitor is initially charged to the voltage of an external power source, and then decoupled from the external power source. The capacitor provides power to an internal processor, and consequently discharges gradually. At the end of a given time interval, the capacitor is discharged to a fixed voltage, then charged to the supply voltage. In this manner the power consumed by charging of the capacitor is decoupled from the power consumed by the processor. If the capacitor drops below a threshold voltage before processing is completed, the processor is halted. To optimize the available processing time, the time interval before discharging the capacitor to the fixed voltage is dynamically adjusted to reduce the time that the processor is halted.

Abstract: An arrangement with a microprocessor, particularly a microprocessor for use in a chip card is described. The arrangement includes a microprocessor which is connected to at least a USB interfaces and an ISO interface for exchanging data signals. A selection unit within the microprocessor may be configured to select between the USB and ISO interfaces, and a switching unit within the microprocessor may be configured to subsequently switch between the USB and ISO interfaces by initiating an internal reset of the microprocessor.

Abstract: A data carrier (4) for the contactless communication of communication information (KD) with a transmitting/receiving station (1) includes receiving circuit (7) for receiving an HF signal (HF) containing the communication information (KD) from the transmitting/receiving station (1), and processing circuit (10) for processing the received communication information (KD), and supply voltage generating circuit (13) for rectifying the received HF signal (HF) and for energizing the processing circuit (10) with a supply voltage (UV), and reset circuit (14) for resetting, when the supply voltage (UV) decreases below a reset voltage value (UR), the processing performed by the processing circuit (10), the reset circuit (14) now being adapted to interrupt the processing of the communication information (KD) by the processing circuit (10) at least partially when the supply voltage (UV) decreases below an interruption voltage value (UU), the interruption voltage value (UU) being greater than the reset voltage value (UR).

Abstract: The invention relates to a method and a configuration for the transmission of signals from generating functional units to processing functional units of electrical circuits, which can be used to prevent the interception of information being exchanged between two functional units that are located separately in the layout.

Abstract: The invention relates to a method and an arrangement for increasing the security of circuits against unauthorized access, both of which can be used in particular to improve the security of cards, and particularly smart cards, against attacks in which the differential power analysis approach (DPA) is followed.

Abstract: A method is described for multiplying two factors from the Galois field GF (2m*p), where each of the factors can be represented as a vector of p sub-blocks with a width of m bits and p, m are positive integers greater than 1, which method includes the following steps:

Abstract: The invention relates to a method and an arrangement for protecting digital parts of circuits, which method and arrangement may be used in particular to protect memory units in such digital circuits, and particularly in smart-card controllers, that contain secret data, against attacks in which the approach adopted is to change digital parts of circuits, and particularly the digital part of a smart-card controller, to an undefined state by brief voltage drops, e.g. by light-flash attacks.

Abstract: An arrangement with a microprocessor, particularly a microprocessor for use in a chip card is described.

Abstract: A digital microelectronic circuit comprises a clocked data-processing unit (1) and a converting unit (2) which reads in data present at the output of the data-processing unit, performs a predetermined converting operation on the data and passes on the converted data. The converting unit is realized in an asynchronous logic circuit, such that the period of time for performing the converting operation is shorter than the shortest time interval to the next change of the data present at the output of the data-processing unit. In this way, fast, serial synchronous processes can be parallelized from the point of view of the slow synchronous system in synchronous systems which are slow relative thereto by using asynchronous logics, without a further high-frequency clock system being required.

Abstract: In a data carrier (2) for the communication of communication data (KD1, KD2) with a base station, having processing means (4) for the processing of communicated communication data (KD1, KD2), and having voltage supply means (5) which are arranged to receive an external supply voltage (UEXT) applied to the data carrier during a charging time interval (TL) until a turn-on instant (te1, te2, te3) and which are adapted to supply an internal supply voltage (UINT) to the processing means (4), decoupled from the external supply voltage (UEXT), during a consumption time interval (TV1, TV2, TV3) starting at the turn-on instant (te1, te2, te3), the processing means (4) being adapted to interrupt the processing from an interruption instant (tu1, tu2, tu3), when the internal supply voltage (UINT) decreases below a threshold voltage (US), till the turn-on instant (te1, te2, te3), time measurement means (12) are now provided, which time measurement means are adapted to measure a processing time interval (TP1, TP2, TP3) def

Abstract: A data carrier (4) for the contactless communication of communication information (KD) with a transmitting/receiving station (1) includes receiving means (7) for receiving an HF signal (HF) containing the communication information (KD) from the transmitting/receiving station (1), and processing means (10) for processing the received communication information (KD), and supply voltage generating means (13) for rectifying the received HF signal (HF) and for energizing the processing means (10) with a supply voltage (UV), and reset means (14) for resetting, when the supply voltage (UV) decreases below a reset voltage value (UR), the processing performed by the processing means (10), the reset means (14) now being adapted to interrupt the processing of the communication information (KD) by the processing means (10) at least partially when the supply voltage (UV) decreases below an interruption voltage value (UU), the interruption voltage value (UU) being greater than the reset voltage value (UR).

Abstract: The present invention relates to a data processing device (100), notably a chip card, which includes an integrated circuit (10) and a power supply. The power supply includes a voltage converter (12) which converts an output current Iaus (46), powering the integrated circuit (10), into a pulsed input current Iein (44), where Vaus≦Vein.

Abstract: A circuit arrangement for delivering a supply current for an electronic circuit from a supply voltage source has a controllable current source arrangement which can be switched over so as to deliver a first and a second predetermined constant current. The second constant current is larger than the first constant current. An input of the controllable current source arrangement is connected to the supply voltage source and an output of the controllable current source arrangement is connected to an energy storage element and to the electronic circuit. The circuit arrangement further has a first reference voltage source for preparing a first and a second reference voltage. The second reference voltage is higher than the first reference voltage.