Patents by Inventor Markus Gail
Markus Gail has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210097798Abstract: A consumable component apparatus including a receptacle region for receiving configured to receive a substance or material which is consumed under the control of a consumer device, an authentication circuit configured to authenticate the consumer device, and a switch coupled to the authentication circuit. The authentication circuit is configured to control the switch in such a way that the consumable component apparatus is activatable only if the consumer device is authenticated by means of the authentication circuit, and that the consumable component apparatus is deactivated if the consumer device is not authenticated by means of the authentication circuit.Type: ApplicationFiled: September 28, 2020Publication date: April 1, 2021Inventors: Peter Laackmann, Markus Gail
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Patent number: 9471793Abstract: An embedded security module includes a security processor, volatile and non-volatile memory, and an interface. The security processor includes transistors formed in one or more semiconductor layers of a semiconductor die, and implements one or more security-related functions on data and/or code accessed by the security processor. The volatile memory is fabricated on the same semiconductor die as the security processor and stores the data and/or code accessed by the security processor. The non-volatile memory includes non-volatile storage cells disposed above each semiconductor layer of the semiconductor die, and securely stores at least one of the data and/or code accessed by the security processor and security information relating to the data and/or code accessed by the security processor. The interface is fabricated on the same semiconductor die as the security processor and provides a communication interface for the security processor.Type: GrantFiled: December 20, 2013Date of Patent: October 18, 2016Assignee: Infineon Technologies AGInventors: Markus Gail, Gerd Dirscherl, Marcus Janke
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Patent number: 8879733Abstract: A random bit stream generator includes an internal state memory for storing a current internal state of the random bit stream generator and a periodic bit sequence generator configured to provide a periodic bit sequence. An output function receives a bit sequence portion of the periodic bit sequence and a first internal state portion of the current internal state. A new output bit of the random bit stream is determined, by the output function, based on a Boolean combination of the bit sequence portion and the first internal state portion. A feedback arrangement feeds the new output bit back to the internal state memory by performing a Boolean combination involving the new output bit and a second internal state portion of the current internal state to determine a next internal state of the random bit generator.Type: GrantFiled: July 10, 2012Date of Patent: November 4, 2014Assignee: Infineon Technologies AGInventors: Rainer Goettfert, Berndt Gammel, Markus Gail
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Patent number: 8861725Abstract: A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.Type: GrantFiled: July 10, 2012Date of Patent: October 14, 2014Assignee: Infineon Technologies AGInventors: Rainer Goettfert, Berndt Gammel, Markus Gail, Wieland Fischer
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Publication number: 20140223569Abstract: An embedded security module includes a security processor, volatile and non-volatile memory, and an interface. The security processor includes transistors formed in one or more semiconductor layers of a semiconductor die, and implements one or more security-related functions on data and/or code accessed by the security processor. The volatile memory is fabricated on the same semiconductor die as the security processor and stores the data and/or code accessed by the security processor. The non-volatile memory includes non-volatile storage cells disposed above each semiconductor layer of the semiconductor die, and securely stores at least one of the data and/or code accessed by the security processor and security information relating to the data and/or code accessed by the security processor. The interface is fabricated on the same semiconductor die as the security processor and provides a communication interface for the security processor.Type: ApplicationFiled: December 20, 2013Publication date: August 7, 2014Applicant: Infineon Technologies AGInventors: Markus Gail, Gerd Dirscherl, Marcus Janke
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Publication number: 20140019502Abstract: A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.Type: ApplicationFiled: July 10, 2012Publication date: January 16, 2014Applicant: Infineon Technologies AGInventors: Rainer Goettfert, Berndt Gammel, Markus Gail, Wieland Fischer
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Publication number: 20140016778Abstract: A random bit stream generator includes an internal state memory for storing a current internal state of the random bit stream generator and a periodic bit sequence generator configured to provide a periodic bit sequence. An output function receives a bit sequence portion of the periodic bit sequence and a first internal state portion of the current internal state. A new output bit of the random bit stream is determined, by the output function, based on a Boolean combination of the bit sequence portion and the first internal state portion. A feedback arrangement feeds the new output bit back to the internal state memory by performing a Boolean combination involving the new output bit and a second internal state portion of the current internal state to determine a next internal state of the random bit generator.Type: ApplicationFiled: July 10, 2012Publication date: January 16, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Rainer Goettfert, Berndt Gammel, Markus Gail
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Publication number: 20100182147Abstract: A security circuit comprising including a sensor located remotely from a central alarm handler and configured to sense an attack, and a phase-change memory cell coupled to and located remotely with the sensor, and configured to store an alarm event when the attack is sensed.Type: ApplicationFiled: January 20, 2009Publication date: July 22, 2010Applicant: INFINEON TECHNOLOGIES A.G.Inventors: Stefan Rueping, Thomas Nirschl, Ronald Kakoschke, Franz Josef Bruecklmayr, Markus Gail, Berndt Gammel, Gerd Dirscherl
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Patent number: 7634640Abstract: Data processing apparatus having an execution unit, a flow controller having a program counter, and a program counter sensor, which is connected to a data bus and to the program counter. The program counter sensor has a logic unit that ascertains the address of an instruction which is to be executed next from data transferred via the data bus, and a comparator, which compares the ascertained address with a content of the program counter and triggers an alarm signal if there is any discrepancy.Type: GrantFiled: February 24, 2005Date of Patent: December 15, 2009Assignee: Infineon Technologies AGInventors: Markus Gail, Jan Otterstedt
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Publication number: 20050182990Abstract: Data processing apparatus having an execution unit, a flow controller having a program counter, and a program counter sensor, which is connected to a data bus and to the program counter. The program counter sensor has a logic unit that ascertains the address of an instruction which is to be executed next from data transferred via the data bus, and a comparator, which compares the ascertained address with a content of the program counter and triggers an alarm signal if there is any discrepancy.Type: ApplicationFiled: February 24, 2005Publication date: August 18, 2005Applicant: Infineon Technologies AGInventors: Markus Gail, Jan Otterstedt
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Patent number: 6708890Abstract: A circuit configuration includes at least one nonvolatile, electrically erasable and writable memory area. Each memory area is assigned a nonvolatile, electrically writable and erasable flag memory, which is connected through an address line, a programming line and an authentication line to the assigned memory area, a programming voltage source and a data verification circuit. In the event of an alteration in the content of a memory area, the state of the associated flag memory is changed and, after verification of the programmed memory area content, the flag memory is returned to its basic state.Type: GrantFiled: March 30, 2001Date of Patent: March 23, 2004Assignee: Infineon Technologies AGInventors: Markus Gail, Wolfgang Pockrandt, Armin Wedel, Erwin Hess
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Publication number: 20010030239Abstract: A circuit configuration includes at least one nonvolatile, electrically erasable and writable memory area. Each memory area is assigned a nonvolatile, electrically writable and erasable flag memory, which is connected through an address line, a programming line and an authentication line to the assigned memory area, a programming voltage source and a data verification circuit. In the event of an alteration in the content of a memory area, the state of the associated flag memory is changed and, after verification of the programmed memory area content, the flag memory is returned to its basic state. A method for authenticating the content of a memory area is also provided.Type: ApplicationFiled: March 30, 2001Publication date: October 18, 2001Inventors: Markus Gail, Wolfgang Pockrandt, Armin Wedel, Erwin Hess