Patents by Inventor Markus Hofsäss

Markus Hofsäss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7484189
    Abstract: A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by means of allocation criteria. An evaluation criterion allocated to the class which was allocated to the section is then applied to the section in order to obtain an evaluation result. Each section is then identified as potentially faulted in dependence on the evaluation result.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: January 27, 2009
    Assignee: Qimonda AG
    Inventors: Markus Hofsäss, Eva-Maria Nash
  • Patent number: 7393614
    Abstract: A set of at least two masks for the projection of structure patterns coordinated with one another by a projection system into the same photosensitive layer of a semiconductor wafer, in which the set of at least two masks includes a primary mask having an opaque structure element, which is formed at a first position on the first mask. A second mask of the set, for example a trimming mask, which is assigned to the first mask, can have a semitransparent region assigned to the structure element of the first mask. The semitransparent region can be formed at the same position on the second mask as the opaque structure element on the first mask. With the aid of the suitable choice of the transparency of the semitransparent region, it is possible to enable an undesirable resist region to be trimmed away for enlargement of a process window during exposure of the photosensitive layer on the semiconductor wafer.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: July 1, 2008
    Assignee: Infineon Technologies AG
    Inventors: Roderick Köhle, Rainer Pforr, Jörg Thiele, Wolfgang Dettmann, Markus Hofsäss, Mario Hennig
  • Publication number: 20080147373
    Abstract: According to one aspect, a method for analyzing the design of an integrated circuit comprises performing a simulation of the integrated circuit design to obtain simulation results and automatically associating the obtained simulation results to layout elements of the integrated circuit.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 19, 2008
    Inventors: Thomas Roessler, Markus Hofsaess
  • Publication number: 20070192754
    Abstract: Embodiments of the invention provide a method for treating errors during the checking of a design of an integrated circuit. In one embodiment, the method includes checking the design of the integrated circuit for errors using predetermined design rules, wherein the design includes a plurality of cells, detecting a design error when the design deviates from the predetermined design rules, writing the design error into a design error file, wherein at least one detected design error is written into a design waiver file if the design error is allowed as an allowed design error in spite of the deviation from the predetermined rules, and storing the allowed design error in the design waiver file with specification of a cell in which the design error occurs.
    Type: Application
    Filed: February 14, 2006
    Publication date: August 16, 2007
    Inventor: Markus Hofsaess
  • Publication number: 20060282720
    Abstract: Methods and systems for the determination of the function and of the position information of fuses from a schematic and/or a network list and a layout. A repair process is aided with this position information.
    Type: Application
    Filed: April 3, 2006
    Publication date: December 14, 2006
    Inventors: Markus Hofsaess, Bermherd Ruf, Florian Schnabel
  • Patent number: 6730463
    Abstract: A photoresist layer on a substrate wafer is exposed in first sections with a first exposure radiation and in second sections with a second exposure radiation that is phase-shifted by 180°. The first and second sections adjoin one another in boundary regions in which the photoresist layer is artificially not sufficiently exposed. Where a distance between these boundary regions is smaller than a photolithographically critical, least distance, the photoresist layer is exposed, at a first boundary region, with a third exposure radiation and at a second boundary region with a fourth exposure radiation phase-shifted by 180°. A trim mask provided for the process has a first translucent region and a second translucent region. The first light-transparent region and the second light-transparent region are fashioned such that the light passing through the first light-transparent region and the light passing through the second light-transparent region has a phase displacement of 180°.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: May 4, 2004
    Assignee: Infineon Technologies AG
    Inventors: Michael Heissmeier, Markus Hofsäss, Burkhard Ludwig, Molela Moukara, Christoph Nölscher
  • Patent number: 6680151
    Abstract: An alternating phase mask is described in which a propagation of a T phase conflict which occurs in the case of a T pattern structure is avoided by producing a phase jump at one of the 90° corners of the T pattern structure. First and second transparent area segments, which produce a mutual phase difference of 180°, are separated by a narrow slot running approximately at 45° toward the corner of the T pattern structure. The structure containing the transparent area segments, which are separated by the slot running at 45°, can also be provided at the other corner of the T structure providing a solution for each T conflict. The trimming mask for eliminating the dark line artificially produced by the 180° phase jump is a conventional mask and requires no additional coloration. Moreover, alignment errors are minimal on account of the small number of trimming openings.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: January 20, 2004
    Assignee: Infineon Technologies AG
    Inventors: Michael Heissmeier, Markus Hofsäss, Burkhard Ludwig, Molela Moukara, Christoph Nölscher