Patents by Inventor Markus Koesler
Markus Koesler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908384Abstract: A circuit for generating a PWM signal includes a shift register having a plurality of clock-controlled register units. Each clock-controlled register unit has an input and an output. The circuit also includes a write unit configured to set the outputs of the register units each to a designated logical value. The circuit further includes a clock generator configured to drive the register units with a common clock signal. The register units are connected in series. The shift register is configured to output the PWM signal at an output contact. The PWM signal is a chronological sequence of the logical values set in the register units, the PWM signal assumes each of the logical values with the duration of one clock of the clock signal, the clock signal is cyclic, during one cycle the duration of successive clocks changes, and the clock signal is identical per cycle.Type: GrantFiled: April 27, 2020Date of Patent: February 20, 2024Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Christopher Soell, Markus Koesler, Jens Richter
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Patent number: 11776461Abstract: A circuit for generating a PWM signal includes a shift register having a plurality of clock-controlled register units. Each clock-controlled register unit has an input and an output. The circuit also includes a write unit configured to set the outputs of the register units each to a designated logical value. The circuit further includes a clock generator configured to drive the register units with a common clock signal. The register units are connected in series. The shift register is configured to output the PWM signal at an output contact. The PWM signal is a chronological sequence of the logical values set in the register units, the PWM signal assumes each of the logical values with the duration of one clock of the clock signal, the clock signal is cyclic, during one cycle the duration of successive clocks changes, and the clock signal is identical per cycle.Type: GrantFiled: April 27, 2020Date of Patent: October 3, 2023Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Christopher Soell, Markus Koesler, Jens Richter
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Patent number: 11513804Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.Type: GrantFiled: September 23, 2020Date of Patent: November 29, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Markus Koesler, Johann Zipperer, Christian Wiencke, Wolfgang Lutsch
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Patent number: 11449341Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.Type: GrantFiled: September 9, 2019Date of Patent: September 20, 2022Assignee: Texas Instruments IncorporatedInventors: Marko Krüger, Steven Bartling, Markus Kösler
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Publication number: 20220237106Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Inventors: Jason Lynn PECK, Gary A. COOPER, Markus KOESLER
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Publication number: 20220197780Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: ApplicationFiled: March 11, 2022Publication date: June 23, 2022Inventors: Jason Lynn PECK, Gary A. COOPER, Markus KOESLER
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Publication number: 20220189384Abstract: A circuit for generating a PWM signal includes a shift register having a plurality of clock-controlled register units. Each clock-controlled register unit has an input and an output. The circuit also includes a write unit configured to set the outputs of the register units each to a designated logical value. The circuit further includes a clock generator configured to drive the register units with a common clock signal. The register units are connected in series. The shift register is configured to output the PWM signal at an output contact. The PWM signal is a chronological sequence of the logical values set in the register units, the PWM signal assumes each of the logical values with the duration of one clock of the clock signal, the clock signal is cyclic, during one cycle the duration of successive clocks changes, and the clock signal is identical per cycle.Type: ApplicationFiled: April 27, 2020Publication date: June 16, 2022Inventors: Christopher SOELL, Markus KOESLER, Jens RICHTER
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Publication number: 20220130878Abstract: A diode array with at least two image elements. The diode array includes a distribution transistor as well as a feed line for receiving a reference current and a first supply terminal coupled to the distribution transistor for supplying the distribution transistor. A diode and an input transistor are provided for each image element, each of which is coupled to the diode for supplying the diode. The distribution transistor forms a distribution current mirror with the respective input transistor of at least two image elements.Type: ApplicationFiled: February 20, 2020Publication date: April 28, 2022Inventors: Christopher SÖLL, Jens RICHTER, Markus KÖSLER
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Patent number: 11307965Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: GrantFiled: September 3, 2020Date of Patent: April 19, 2022Assignee: Texas Instruments IncorporatedInventors: Jason Lynn Peck, Gary A. Cooper, Markus Koesler
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Patent number: 11294794Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: GrantFiled: August 31, 2020Date of Patent: April 5, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jason Lynn Peck, Gary A. Cooper, Markus Koesler
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Publication number: 20220083455Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: ApplicationFiled: November 30, 2021Publication date: March 17, 2022Inventors: Jason Lynn PECK, Gary A. COOPER, Markus KOESLER
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Patent number: 11216356Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: GrantFiled: August 31, 2020Date of Patent: January 4, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jason Lynn Peck, Gary A. Cooper, Markus Koesler
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Publication number: 20210004236Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.Type: ApplicationFiled: September 23, 2020Publication date: January 7, 2021Inventors: Markus Koesler, Johann Zipperer, Christian Wiencke, Wolfgang Lutsch
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Publication number: 20200401500Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: ApplicationFiled: August 31, 2020Publication date: December 24, 2020Inventors: Jason Lynn PECK, Gary A. COOPER, Markus KOESLER
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Publication number: 20200401501Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Inventors: Jason Lynn PECK, Gary A. COOPER, Markus KOESLER
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Publication number: 20200401499Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: ApplicationFiled: August 31, 2020Publication date: December 24, 2020Inventors: Jason Lynn PECK, Gary A. COOPER, Markus KOESLER
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Patent number: 10795685Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.Type: GrantFiled: April 9, 2019Date of Patent: October 6, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Markus Koesler, Johann Zipperer, Christian Wiencke, Wolfgang Lutsch
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Patent number: 10769050Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: GrantFiled: May 16, 2018Date of Patent: September 8, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jason Lynn Peck, Gary A. Cooper, Markus Koesler
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Patent number: 10761968Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: GrantFiled: May 16, 2018Date of Patent: September 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jason Lynn Peck, Gary A. Cooper, Markus Koesler
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Patent number: 10761967Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.Type: GrantFiled: May 16, 2018Date of Patent: September 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jason Lynn Peck, Gary A. Cooper, Markus Koesler