Patents by Inventor Markus Lachenmayr

Markus Lachenmayr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240025034
    Abstract: A method for providing an enhanced human-machine interface to control a robot, and a device supporting the method is provided. According to one embodiment of the present invention, a method includes: monitoring a manipulation input by a user for an operation of the robot on the enhanced HMI, which is enhanced from a proprietary HMI proprietary to the robot; generating a first program in a first program environment for the enhanced HMI in response to the monitored manipulation; retrieving action information relating to actions to be performed as part of the operation of the robot, wherein the actions are defined in a second program environment for the proprietary HMI; generating a second program in the second program environment corresponding to the first program by using the retrieved action information; and controlling the robot to perform the operation using the second program.
    Type: Application
    Filed: August 19, 2021
    Publication date: January 25, 2024
    Inventors: Markus Lachenmayr, Tudor Ionescu, Joachim Fröhlich
  • Publication number: 20230401297
    Abstract: The present invention relates to the anonymized confirmation of personal user features. A user authenticates the user features to be checked with a separate authentication device. The authentication with a service provider takes place by way of anonymized authentication information.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 14, 2023
    Inventors: Florian Krautwurm, Martin Metzker, Markus Lachenmayr, Tobias Appl, Robin Bollmann
  • Publication number: 20230318870
    Abstract: A computer-implemented method for providing at least one service in a node or process of a cyber-physical system has at least two application modules, wherein a communication between the at least two application modules occurs via respective application interfaces of the at least two application modules, which application interfaces are offered specifically to the particular application module, wherein a particular application interface which is offered specifically to the particular application module represents a communication access to the particular application module. According to the invention, at least the application interfaces of the at least two application modules which are offered specifically to the application module are implemented by a coupling module which establishes the communication between the at least two application modules and which provides the at least one service in an activatable manner.
    Type: Application
    Filed: July 12, 2021
    Publication date: October 5, 2023
    Inventors: Markus Lachenmayr, Joachim Fröhlich, Tudor Ionescu
  • Publication number: 20220197945
    Abstract: Provided is a computer-implemented method for analyzing a transaction log, stored in a computer readable storage medium, wherein the transaction log comprises records of transactions in the range of zero to a plurality of records, wherein each record of transaction comprises at least one action executed during a test and at least one associated recorded criterion, comprising the steps: a. Providing the transaction log and at least one filter criterion; b. Determining records of transactions from the transaction log to be filtered in accordance with the at least one filter criterion; wherein the at least one filter criterion matches the respective associated recorded criterion of the action at least one action of the respective filtered records of transactions of transaction; c. Determining a test verdict based on the filtered records of transactions of transaction; and d. Providing the filtered records of transactions, the test verdict and/or related data as output.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Inventor: Markus Lachenmayr
  • Patent number: 10740098
    Abstract: A method, computer program product, and computer system for providing a comparison result vector of a predefined number of elements w resulting from comparison of multiple vectors of compressed data within a processor comprising registers of same size m is provided. Vector elements of the comparison result vector are stored in a register of the registers. Zero bits are padded between vector elements of each of the comparison result vectors. A compare bit result vector indicative of the vector elements is generated for accessing the results of the comparison in the comparison result vector.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cedric Lichtenau, Silvia M. Mueller, Jens P. Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab, Pavankrishna Ellore Ramesh, Sourabh Chougule
  • Patent number: 10579375
    Abstract: The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cedric Lichtenau, Silvia M. Mueller, Jens P. Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab, Pavankrishna Ellore Ramesh, Sourabh Chougule
  • Publication number: 20190243649
    Abstract: The present disclosure relates a method, computer program product, and computer system to provide a comparison result vector of a predefined number of elements w resulting from comparison of multiple vectors of compressed data within a processor comprising registers of same size m. Vector elements of the comparison result vector are stored in a register of the registers. Zero bits are padded between vector elements of each of the comparison result vectors. A compare bit result vector indicative of the vector elements is generated for accessing the results of the comparison in the comparison result vector.
    Type: Application
    Filed: February 6, 2018
    Publication date: August 8, 2019
    Inventors: Cedric Lichtenau, Silvia M. Mueller, Jens P. Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab, Pavankrishna Ellore Ramesh, Sourabh Chougule
  • Publication number: 20190243650
    Abstract: The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.
    Type: Application
    Filed: February 6, 2018
    Publication date: August 8, 2019
    Inventors: Cedric Lichtenau, Silvia M. Mueller, Jens P. Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab, Pavankrishna Ellore Ramesh, Sourabh Chougule