Abstract: A component carrier includes a stack with electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures have a higher density connection region and a lower density connection region, and a first component and a second component which are surface mounted on the stack. The first component and the second component are electrically coupled with each other by the higher density connection region.

Abstract: A component carrier includes a stack with electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures have a higher density connection region and a lower density connection region, and a first component and a second component which are surface-mounted on the stack. The first component and the second component are electrically coupled with each other by the higher density connection region.

Abstract: A method for manufacturing a component carrier includes i) providing a metal layer, in particular a copper layer; ii) forming a film on the metal layer; iii) patterning the film in order to expose a part of the metal layer; iv) carrying out a first etch, thereby thinning the film and removing a further part of the exposed metal layer; and thereafter v) carrying out a second etch, thereby forming at least one metal trace that is spatially separated from the metal layer. A component carrier made by the method is further described.

Abstract: An integrated circuit substrate for surface mounting an integrated circuit component thereon, wherein the integrated circuit substrate comprises a central section, and at least two vertically stacked functional volume sections in the central section, wherein a pitch at an integrated circuit component mounting side of the integrated circuit substrate is not more than 150 ?m.

Abstract: A package comprising an integrated circuit substrate having an exposed substrate pad and having an exposed substrate dielectric, and an electronic component having an integrated circuit, having an exposed component pad and having an exposed component dielectric, wherein the integrated circuit substrate is connected with the electronic component so that there is a direct physical contact between the substrate pad and the component pad and so that there is a direct physical contact between the substrate dielectric and the component dielectric.

Abstract: An integrated circuit substrate for surface mounting an integrated circuit component thereon, wherein the integrated circuit substrate comprises a support structure having at least one hole, and at least two functional inlays placed inside said at least one hole side by side, wherein a pitch at an integrated circuit component mounting side of the integrated circuit substrate is not more than 150 ?m.

Abstract: A component carrier includes a stack with at least one electrically insulating layer structure and electrically conductive layer structures some of which have a first density of trace structures and a second density of connection structures, and a further stack with at least one further electrically insulating layer structure and further electrically conductive layer structures some of which have a third density of further trace structures and a fourth density of further connection structures. A first component is applied to the stack and a second component is embedded in the further stack. The connection structures are respectively connected to the further connection structures. The first density of trace structures is lower than the third density of further trace structures. The stack and the further stack are connected with each other by the connection structures and by the further connection structures. The first component is connected to the second component.

Abstract: A component carrier including a stack having at least one electrically conductive layer structure and a plurality of electrically insulating layer structures. Methods are presented for manufacturing the component carrier where the at least one electrically conductive layer structure is arranged with a vertical connection structure continuously extending vertically through at least two of the plurality of electrically insulating layer structures.

Abstract: A component carrier includes a first stack with an electrically insulating layer structure and an electrically conductive layer structure with a first density of trace structures and a second density of first connection structures, a second stack with a second electrically insulating layer structure and a second electrically conductive layer structure with a third density of second trace structures and a fourth density of second connection structures. A first component is applied to the first stack and a second component is embedded in the second stack. The first connection structures are respectively connected to the second connection structures. The first density of first trace structures is lower than the third density of second trace structures. The first stack and the second stack are connected with each other by the first connection structures and by the second connection structures. The first component is connected to the second component.

Abstract: A component carrier which includes a stack having at least one electrically conductive layer structure, at least one electrically insulating layer structure, and a recess being at least partially formed in the stack, optionally having an electrically conductive coating, and being configured as waveguide, wherein a plurality of edges delimiting the recess are formed by electrically conductive material of the at least one electrically conductive layer structure and/or of the optional electrically conductive coating.

Abstract: The present invention provides a compound semiconductor layered structure comprising: a semiconductor substrate having a bottom surface and a top surface; and a compound semiconductor film on top of said semiconductor substrate, said compound semiconductor film comprising a porous, polycrystalline bottom layer in direct contact with said top surface of said semiconductor substrate, and methods of making the same.

Abstract: The present invention provides compound semiconductor layered structures comprising a semiconductor substrate having a bottom layer and a top layer; and a semiconductor film on top of said semiconductor substrate, said semiconductor film comprising a bottom layer, a core and a top layer, whereby said bottom layer of said semiconductor film is in contact with said top surface of said semiconductor substrate, and wherein said top layer is nonporous. Preferred compound semiconductors further comprise a semiconductor overlayer having a bottom surface layer and a top surface layer, whereby said bottom surface layer of said second semiconductor layer is in contact with said top layer of said semiconductor film. The present invention also provides process for preparing the same.

Abstract: A component carrier includes a stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure and a through hole. An interposer is located in the through hole and has a higher density of connection elements than the stack. A first component is mounted on a first main surface of the interposer and a second component is mounted on a second main surface of the interposer. The first component and the second component are connected via the interposer.

Abstract: A component carrier which includes a stack having at least one electrically conductive layer structure, at least one electrically insulating layer structure, and a recess being at least partially formed in the stack, optionally having an electrically conductive coating, and being configured as waveguide, wherein a plurality of edges delimiting the recess are formed by electrically conductive material of the at least one electrically conductive layer structure and/or of the optional electrically conductive coating.

Abstract: An interposer-type component carrier includes a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; a cavity formed in an upper portion of the stack; an active component embedded in the cavity and having at least one terminal facing upwards; and a redistribution structure having only one electrically insulating layer structure above the component. A method of manufacturing an interposer-type component carrier is also disclosed.

Abstract: A method of compensating misalignment during manufacturing laminate-type component carriers is disclosed. The method includes detecting an image of a region of interest of a component carrier structure during manufacturing the component carriers based on the component carrier structure, identifying a structural feature in the image of the region of interest showing misalignment with respect to a target design, and at least partially compensating the identified misalignment of the structural feature by modifying the target design of at least one correlated structural feature to be manufactured subsequently, wherein the at least one correlated structural feature is correlated to said structural feature showing misalignment.

Abstract: A component carrier includes a stack with electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures have a higher density connection region and a lower density connection region, and a first component and a second component which are surface-mounted on the stack. The first component and the second component are electrically coupled with each other by the higher density connection region.

Abstract: A component carrier includes a stack with at least one electrically insulating layer structure and electrically conductive layer structures some of which have a first density of trace structures and a second density of connection structures, and a further stack with at least one further electrically insulating layer structure and further electrically conductive layer structures some of which have a third density of further trace structures and a fourth density of further connection structures. A first component is applied to the stack and a second component is embedded in the further stack. The connection structures are respectively connected to the further connection structures. The first density of trace structures is lower than the third density of further trace structures. The stack and the further stack are connected with each other by the connection structures and by the further connection structures. The first component is connected to the second component.

Abstract: An arrangement includes a panel configured as a pre-form for manufacturing a plurality of component carriers; a protection layer covering a surface portion of a main surface of the panel, wherein the protection layer is detachable from the surface portion without leaving residues on the panel. A handling tool for handling the panel includes a surface onto which the panel is arrangeable. The panel includes a handling surface, with which the panel is arrangeable onto the handling tool, wherein the handling surface comprises at least part of the surface portion covered by the protection layer.

Abstract: A method for manufacturing a component carrier includes i) providing a metal layer, in particular a copper layer; ii) forming a film on the metal layer; iii) patterning the film in order to expose a part of the metal layer; iv) carrying out a first etch, thereby thinning the film and removing a further part of the exposed metal layer; and thereafter v) carrying out a second etch, thereby forming at least one metal trace that is spatially separated from the metal layer. A component carrier made by the method is further described.