Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

Abstract: The present disclosure relates to a method of operating a hierarchical translation lookaside buffer (TLB). The TLB comprises at least two TLB levels, wherein a given entry of the upper level TLB comprises a portion of bits for indicating related entries in the lower level TLB. The method comprises the following when a TLB miss is encountered for a requested first virtual address. A first table walk is performed to obtain the absolute memory address for the first virtual address. A logical tag is stored. The logical tag comprises the portion of bits that has been identified in association with the first table walk. In response to determining that a concurrent second table walk, of the ongoing first table walk, that has a second virtual address that addresses the same entry in the upper level TLB as the first virtual address is writing in the TLB, the stored logical tag may be incremented. And, the incremented logical tag and the obtained absolute memory address may be stored in the TLB.

Abstract: The present disclosure relates to a method of operating a hierarchical translation lookaside buffer (TLB). The TLB comprises at least two TLB levels, wherein a given entry of the upper level TLB comprises a portion of bits for indicating related entries in the lower level TLB. The method comprises the following when a TLB miss is encountered for a requested first virtual address. A first table walk is performed to obtain the absolute memory address for the first virtual address. A logical tag is stored. The logical tag comprises the portion of bits that has been identified in association with the first table walk. In response to determining that a concurrent second table walk, of the ongoing first table walk, that has a second virtual address that addresses the same entry in the upper level TLB as the first virtual address is writing in the TLB, the stored logical tag may be incremented. And, the incremented logical tag and the obtained absolute memory address may be stored in the TLB.

Abstract: The method includes identifying a register-transfer level design description for a design. The method further includes identifying one or more tests to perform on the register-transfer level design description. The method includes generating a table of commands from the one or more tests to perform on the register-transfer level design description. The method includes generating a register-transfer level design description from the table of commands for at least one of a set of components including: a test driver for the design, a monitor for the design, and a checker for the design, wherein the register-transfer level design description assigns commands in the generated table of commands to be performed by a corresponding component in the set of components. The method includes simulating the identified one or more tests utilizing the generated register-transfer level design descriptions for at least one of the test driver, the checker, and the monitor.

Abstract: The method includes identifying a register-transfer level design description for a design. The method further includes identifying one or more tests to perform on the register-transfer level design description. The method includes generating a table of commands from the one or more tests to perform on the register-transfer level design description. The method includes generating a register-transfer level design description from the table of commands for at least one of a set of components including: a test driver for the design, a monitor for the design, and a checker for the design, wherein the register-transfer level design description assigns commands in the generated table of commands to be performed by a corresponding component in the set of components. The method includes simulating the identified one or more tests utilizing the generated register-transfer level design descriptions for at least one of the test driver, the checker, and the monitor.

Abstract: The method includes identifying a register-transfer level design description for a design. The method further includes identifying one or more tests to perform on the register-transfer level design description. The method includes generating a table of commands from the one or more tests to perform on the register-transfer level design description. The method includes generating a register-transfer level design description from the table of commands for at least one of a set of components including: a test driver for the design, a monitor for the design, and a checker for the design, wherein the register-transfer level design description assigns commands in the generated table of commands to be performed by a corresponding component in the set of components. The method includes simulating the identified one or more tests utilizing the generated register-transfer level design descriptions for at least one of the test driver, the checker, and the monitor.

Abstract: The method includes identifying a register-transfer level design description for a design. The method further includes identifying one or more tests to perform on the register-transfer level design description. The method includes generating a table of commands from the one or more tests to perform on the register-transfer level design description. The method includes generating a register-transfer level design description from the table of commands for at least one of a set of components including: a test driver for the design, a monitor for the design, and a checker for the design, wherein the register-transfer level design description assigns commands in the generated table of commands to be performed by a corresponding component in the set of components. The method includes simulating the identified one or more tests utilizing the generated register-transfer level design descriptions for at least one of the test driver, the checker, and the monitor.

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.

Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.