Abstract: A circuit arrangement is enclosed. The circuit arrangement includes a first electronic circuit; a second electronic circuit; and a coupling circuit connected between the first electronic circuit and the second electronic circuit. The first electronic circuit is at least partially integrated in a first region of a semiconductor layer, the second electronic circuit is at least partially integrated in a second region of the semiconductor layer, and the second region adjoins a first insulating layer formed on a first surface of the semiconductor layer and is electrically insulated from the first region by a second insulating layer. Further, the coupling circuit is arranged in a third insulating layer formed on a second surface of the semiconductor layer and comprises at least two capacitors connected in series.

Abstract: A circuit arrangement is enclosed. The circuit arrangement includes a first electronic circuit; a second electronic circuit; and a coupling circuit connected between the first electronic circuit and the second electronic circuit. The first electronic circuit is at least partially integrated in a first region of a semiconductor layer, the second electronic circuit is at least partially integrated in a second region of the semiconductor layer, and the second region adjoins a first insulating layer formed on a first surface of the semiconductor layer and is electrically insulated from the first region by a second insulating layer. Further, the coupling circuit is arranged in a third insulating layer formed on a second surface of the semiconductor layer and comprises at least two capacitors connected in series.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*103 ?m and less than 1*1012 ?m.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*103 ?m and less than 1*1012 ?m.

Abstract: A circuit arrangement for monitoring an external voltage supply (VBAT1, VBAT2) and for reliable locking of a signal (Z2), which is emitted from a logic circuit (8), at a voltage level (VDD, VSS) of an internal voltage supply, wherein the circuit arrangement has a voltage divider (6, 7), which is connected between a first and a second external supply voltage (VBAT1, VBAT2) and produces a potential level (VLOCK) for a switching signal; a controllable switch (13) which separates the internal voltage supply, which has a first and a second internal supply voltage (VDD, VSS), from the logic circuit (8) in order to deactivate the latter as a function of a locking signal (LOCKP) which is produced from the switching signal; and a high-value resistor (14) by means of which the signal (Z2) which is emitted from the deactivated logic circuit (8) is drawn to the level of one of the two internal supply voltages (VSS).

Abstract: A circuit arrangement for monitoring an external voltage supply (VBAT1, VBAT2) and for reliable locking of a signal (Z2), which is emitted from a logic circuit (8), at a voltage level (VDD, VSS) of an internal voltage supply, wherein the circuit arrangement has a voltage divider (6, 7), which is connected between a first and a second external supply voltage (VBAT1, VBAT2) and produces a potential level (VLOCK) for a switching signal; a controllable switch (13) which separates the internal voltage supply, which has a first and a second internal supply voltage (VDD, VSS), from the logic circuit (8) in order to deactivate the latter as a function of a locking signal (LOCKP) which is produced from the switching signal; and a high-value resistor (14) by means of which the signal (Z2) which is emitted from the deactivated logic circuit (8) is drawn to the level of one of the two internal supply voltages (VSS).