Abstract: A circuit arrangement is enclosed. The circuit arrangement includes a first electronic circuit; a second electronic circuit; and a coupling circuit connected between the first electronic circuit and the second electronic circuit. The first electronic circuit is at least partially integrated in a first region of a semiconductor layer, the second electronic circuit is at least partially integrated in a second region of the semiconductor layer, and the second region adjoins a first insulating layer formed on a first surface of the semiconductor layer and is electrically insulated from the first region by a second insulating layer. Further, the coupling circuit is arranged in a third insulating layer formed on a second surface of the semiconductor layer and comprises at least two capacitors connected in series.

Abstract: A circuit arrangement is enclosed. The circuit arrangement includes a first electronic circuit; a second electronic circuit; and a coupling circuit connected between the first electronic circuit and the second electronic circuit. The first electronic circuit is at least partially integrated in a first region of a semiconductor layer, the second electronic circuit is at least partially integrated in a second region of the semiconductor layer, and the second region adjoins a first insulating layer formed on a first surface of the semiconductor layer and is electrically insulated from the first region by a second insulating layer. Further, the coupling circuit is arranged in a third insulating layer formed on a second surface of the semiconductor layer and comprises at least two capacitors connected in series.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*103 ?m and less than 1*1012 ?m.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*103 ?m and less than 1*1012 ?m.

Abstract: In a method for recording critical parameters for circuit sections of electronic appliances, the critical parameters are represented by status bits in a status register (24). As a result of a change of state for a critical parameter, the associated status bit assumes a new value and retains this value up until a read operation.

Abstract: A circuit arrangement for protection against electrostatic discharge for a field-effect transistor is disclosed. The arrangement includes a first and a second controllable path each having a control terminal. The control terminals of the controllable paths are coupled to a source terminal of the field-effect transistor. A first terminal of the first controllable path is connected to a control terminal of the transistor, and a first terminal of the second controllable path is connected to a bulk terminal of the unipolar transistor. Second terminals of the controllable paths are connected to the drain terminal. A voltage regulating device includes the circuit arrangement and a comparator configured to generate a control signal in a manner dependent on a difference between two signals applied thereto. A control output of the comparator is coupled to the control terminal of the transistor.

Abstract: A circuit arrangement for monitoring an external voltage supply (VBAT1, VBAT2) and for reliable locking of a signal (Z2), which is emitted from a logic circuit (8), at a voltage level (VDD, VSS) of an internal voltage supply, wherein the circuit arrangement has a voltage divider (6, 7), which is connected between a first and a second external supply voltage (VBAT1, VBAT2) and produces a potential level (VLOCK) for a switching signal; a controllable switch (13) which separates the internal voltage supply, which has a first and a second internal supply voltage (VDD, VSS), from the logic circuit (8) in order to deactivate the latter as a function of a locking signal (LOCKP) which is produced from the switching signal; and a high-value resistor (14) by means of which the signal (Z2) which is emitted from the deactivated logic circuit (8) is drawn to the level of one of the two internal supply voltages (VSS).

Abstract: A circuit for amplifying an input voltage (VIN) into an output voltage (VOUT) with an overall gain factor, which is a product of a first gain factor (S) and a second gain factor (R1), comprises means for generating an intermediate signal (I2) from the input voltage (VIN) and the first gain factor (S) and means for generating the output voltage (VOUT) from the intermediate signal (I2) and the second gain factor (R1). The first gain factor (S) and the second gain factor (R1) have opposite temperature dependencies.

Abstract: A circuit for driving an external FET has a differential amplification stage supplied by a first and second operating potential. An output load resistor is included in a current flow path in which the current is controlled by the voltage between two input terminals of the amplification stage. The current is substantially independent of variations of the first or second operating potentials. The output load resistor is connected between the gate and the source of the external FET 12.

Abstract: A circuit arrangement for monitoring an external voltage supply (VBAT1, VBAT2) and for reliable locking of a signal (Z2), which is emitted from a logic circuit (8), at a voltage level (VDD, VSS) of an internal voltage supply, wherein the circuit arrangement has a voltage divider (6, 7), which is connected between a first and a second external supply voltage (VBAT1, VBAT2) and produces a potential level (VLOCK) for a switching signal; a controllable switch (13) which separates the internal voltage supply, which has a first and a second internal supply voltage (VDD, VSS), from the logic circuit (8) in order to deactivate the latter as a function of a locking signal (LOCKP) which is produced from the switching signal; and a high-value resistor (14) by means of which the signal (Z2) which is emitted from the deactivated logic circuit (8) is drawn to the level of one of the two internal supply voltages (VSS).

Abstract: The invention relates to a method for adjusting a BGR circuit. In a first adjustment step, an offset adjustment of a voltage differential amplifier is performed at a predetermined temperature. In a second adjustment step, the reference voltage generated by the BGR circuit is regulated to as predetermined value of the reference voltage at the predetermined temperature by setting a variable resistance of an external circuitry of the voltage differential amplifier.