Patents by Inventor Markus Neubert

Markus Neubert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260060153
    Abstract: A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.
    Type: Application
    Filed: October 30, 2025
    Publication date: February 26, 2026
    Inventors: Peter Luniewski, Markus Neubert, Michael Fuegl, Waldemar Jakobi, Michael Leipenat, Egbert Lamminger
  • Patent number: 12489040
    Abstract: A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: December 2, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Peter Luniewski, Markus Neubert, Michael Fuegl, Waldemar Jakobi, Michael Leipenat, Egbert Lamminger
  • Publication number: 20240243042
    Abstract: A power semiconductor module includes: an electrically insulative frame; a plurality of power semiconductor dies housed within the electrically insulative frame and electrically interconnected to form a power electronics circuit; an active temperature sensor die housed within the electrically insulative frame and including an integrated current source; a first temperature sense terminal electrically connected to a first contact pad of the active temperature sensor die; and a second temperature sense terminal electrically connected to a second contact pad of the active temperature sensor die. A discrete power semiconductor device and methods of producing the module and discrete device are also described.
    Type: Application
    Filed: January 16, 2023
    Publication date: July 18, 2024
    Inventors: Tillmann Walther, Markus Neubert, Andrey Kravchenko, Christian Schweikert
  • Publication number: 20240079297
    Abstract: A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Peter Luniewski, Markus Neubert, Michael Fuegl, Waldemar Jakobi, Michael Leipenat, Egbert Lamminger