Abstract: A power system having: a DC bus, a plurality of power modules, each including a capacitor, each power module being connected to the DC bus in parallel with the other power modules, a plurality of arc suppressing devices configured to short circuit the DC bus in case of a fault on the DC bus, a plurality of current sensors, each being arranged to measure current between the DC bus and a DC side of a respective power module, and a control system associating each current sensor with an arc suppressing device of the plurality of arc suppressing devices, wherein the control system is configured to, only when at least two of the current sensors simultaneously measure a current higher than a threshold current, trigger the arc suppressing device or arc suppressing devices associated with the at least two current sensors to short circuit the DC bus.

Abstract: A method and an apparatus for determining switching delay times of power semiconductor switch components in parallel connected half bridge legs in which two or more power semiconductor switches are controlled in parallel. The method includes providing a gate control signal to gate drivers of the parallel connected power semiconductor switch components, determining collector to emitter voltages of the parallel connected power semiconductor switch components, and determining separate delay times for each of the parallel connected power semiconductor switch components based on the time instant of the gate control signal and the determined collector to emitter voltages or time derivatives of the determined collector to emitter voltages.

Abstract: A method and an apparatus for determining switching delay times of power semiconductor switch components in parallel connected half bridge legs in which two or more power semiconductor switches are controlled in parallel. The method includes providing a gate control signal to gate drivers of the parallel connected power semiconductor switch components, determining collector to emitter voltages of the parallel connected power semiconductor switch components, and determining separate delay times for each of the parallel connected power semiconductor switch components based on the time instant of the gate control signal and the determined collector to emitter voltages or time derivatives of the determined collector to emitter voltages.

Abstract: A gate drive circuit adapted to control a power semiconductor component, the gate drive circuit comprising a gate driver connectable to a positive auxiliary voltage and to a negative auxiliary voltage, the gate drive circuit comprising a feedback circuit having an inductive coupling element for providing a feedback signal, wherein one end of the feedback circuit having the inductive coupling element is connected to a known reference potential and the other end of the feedback circuit is connected to the gate driver, and the inductive coupling element is inductively coupled to the main current path of the power semiconductor component for providing feedback signal to the gate driver based on the change rate of the current of the power semiconductor component for limiting the change rate of the current of the power semiconductor component.