Abstract: In a method for producing a sensor arrangement and the resulting sensor arrangement, a sensor is provided on or in a chip and the chip is covered with a protective cover, the cover being an interface between the sensor and the environment. An adhesive layer is provided between the chip and the protective cover, the adhesive layer alone or together with the protective cover being an interface between the sensor and the environment. The protective cover and/or the adhesive layer may have a channel formed therein, the channel functioning as the reception channel for a sensor. In an alternative embodiment, the protective cover placed on a wafer with several chips, and the wafer is cut up to produce the individual chips with the protective cover. Thus, a sensor arrangement may have the protective cover applied to the individual chip after the chip is cut from the wafer, or the protective cover may be applied to the wafer, and the wafer and cover are then cut up into the individual chips and corresponding covers.

Abstract: The invention relates to integrated circuits comprising a monolithically integrated logic IC and a monolithically integrated interface circuit that is conductively connected to the logic IC. The electrical properties of said interface circuit are programmable. The interface circuit also has a lower integration density than the logic IC, and comprises monitoring modules for monitoring the logic ICs.

Abstract: An integrated circuit comprises a package and having adjacent connection pins on two opposite sides of the package, with every second connection pin being inwardly bent so that the connection pins are offset. The ends of the inwardly bent connection pins and the ends of the outer connection pins each lie on a straight line, where the offset connection pins are bent by different angles out of the plane of the package.

Abstract: A method for testing a chip with a package having connecting pins and mounting the package on a board combines the advantages of a package with inline connecting pins with that of a package with offset connecting pins. The package with inline connecting is inserted into a socket for testing. Before mounting on the board, at least one connecting pin, preferably every second connecting pin, of the package is bent inward by a bending tool to achieve an offset arrangement of the connecting pins. The package is preferably mounted on the board using the bending tool. Since every second connecting pin is not bent inward immediately before insertion of the connecting pins, no subsequent corrective alignment of the offset connecting pins is required.

Abstract: A carrier device for a monolithic integrated circuit has portions for the connection of bonding wires in the form of pedestals that rise above a chip connection area on the carrier device and have steep sides.

Abstract: The invention relates to the fabrication and testing of a chip with a package (2) having connecting pins (1) as well as to mounting the package (2) on a board (5), whereby in order to combine the advantages of a package (2) with inline connecting pins (1) with the advantages of a package (2) with offset connecting pins (11, 12), the package (2) is fabricated with inline connecting pins (1) and inserted into a test socket (3) for testing. Immediately before mounting on the board (5), at least one connecting pin, preferably every second connecting pin (12), of the package (2) is bent inward by a bending tool (6) so as to achieve an offset arrangement of the connecting pins (11, 12). The package (2) is preferably mounted on the board (5) using the bending tool (6). A simple, inexpensively produced test socket (3) is sufficient for the purpose of testing the chip. An inexpensively produced guide brace (4), for example, is suitable as a packaging means.

Abstract: The invention relates to the fabrication and testing of a chip with a package (2) having connecting pins (1) as well as to mounting the package (2) on a board (5), whereby in order to combine the advantages of a package (2) with inline connecting pins (1) with the advantages of a package (2) with offset connecting pins (11, 12), the package (2) is fabricated with inline connecting pins (1) and inserted into a test socket (3) for testing. Immediately before mounting on the board (5), at least one connecting pin, preferably every second connecting pin (12), of the package (2) is bent inward by a bending tool (6) so as to achieve an offset arrangement of the connecting pins (11, 12). The package (2) is preferably mounted on the board (5) using the bending tool (6). A simple, inexpensively produced test socket (3) is sufficient for the purpose of testing the chip. An inexpensively produced guide brace (4), for example, is suitable as a packaging means.

Abstract: The invention relates to the fabrication and testing of a chip with a package (2) having connecting pins (1) as well as to mounting the package (2) on a board (5), whereby in order to combine the advantages of a package (2) with inline connecting pins (1) with the advantages of a package (2) with offset connecting pins (11, 12), the package (2) is fabricated with inline connecting pins (1) and inserted into a test socket (3) for testing. Immediately before mounting on the board (5), at least one connecting pin, preferably every second connecting pin (12), of the package (2) is bent inward by a bending tool (6) so as to achieve an offset arrangement of the connecting pins (11, 12). The package (2) is preferably mounted on the board (5) using the bending tool (6). A simple, inexpensively produced test socket (3) is sufficient for the purpose of testing the chip. An inexpensively produced guide brace (4), for example, is suitable as a packaging means.

Abstract: The invention relates to a method for producing a sensor (1), wherein a carrier chip (2) is produced. Said chip is provided with a sensor structure (3) comprising an active sensor surface (4). A material (9) capable of flowing is applied onto carrier chips (2) in such a way that the sensor structure (3) has a thinner layer thickness on said active sensor surface (4) than on the area of the carrier chip (2) which borders on the active sensor surface (4). The material (9) which is capable of flowing is hardened thereafter. The hardened material (9) is subsequently removed by chemical means from the surface which faces said carrier chip (2) until the active sensor surface of the sensor structure is layed bare.

Abstract: In a method for producing a sensor arrangement and the resulting sensor arrangement, a sensor is provided on or in a chip and the chip is covered with a protective cover, the cover being an interface between the sensor and the environment. An adhesive layer is provided between the chip and the protective cover, the adhesive layer alone or together with the protective cover being an interface between the sensor and the environment. The protective cover and/or the adhesive layer may have a channel formed therein, the channel functioning as the reception channel for a sensor. In an alternative embodiment, the protective cover placed on a wafer with several chips, and the wafer is cut up to produce the individual chips with the protective cover. Thus, a sensor arrangement may have the protective cover applied to the individual chip after the chip is cut from the wafer, or the protective cover may be applied to the wafer, and the wafer and cover are then cut up into the individual chips and corresponding covers.

Abstract: The invention relates to the fabrication and testing of a chip with a package (2) having connecting pins (1) as well as to mounting the package (2) on a board (5), whereby in order to combine the advantages of a package (2) with inline connecting pins (1) with the advantages of a package (2) with offset connecting pins (11, 12), the package (2) is fabricated with inline connecting pins (1) and inserted into a test socket (3) for testing. Immediately before mounting on the board (5), at least one connecting pin, preferably every second connecting pin (12), of the package (2) is bent inward by a bending tool (6) so as to achieve an offset arrangement of the connecting pins (11, 12). The package (2) is preferably mounted on the board (5) using the bending tool (6). A simple, inexpensively produced test socket (3) is sufficient for the purpose of testing the chip. An inexpensively produced guide brace (4), for example, is suitable as a packaging means.

Abstract: The invention relates to a method for producing a sensor (1), wherein a carrier chip (2) is produced. Said chip is provided with a sensor structure (3) comprising an active sensor surface (4). A material (9) capable of flowing is applied onto carrier chips (2) in such a way that the sensor structure (3) has a thinner layer thickness on said active sensor surface (4) than on the area of the carrier chip (2) which borders on the active sensor surface (4). The material (9) which is capable of flowing is hardened thereafter. The hardened material (9) is subsequently removed by chemical means from the surface which faces said carrier chip (2) until the active sensor surface of the sensor structure is layed bare.