Abstract: An integrated semiconductor memory device includes a memory cell array with sense amplifiers that are combined in groups within the memory cell array. Each sense amplifier is associated with one data connection, the association varying on the basis of area within the memory cell array. When a memory cell is read, further adjacent memory cells besides the memory cell which is to be read are read, so that data are produced at all the data connections. To this end, the sense amplifiers in a group are activated together. To establish which sense amplifier within a group of sense amplifiers has a signaling connection to which data connection, individual sense amplifiers in a group can be deactivated specifically, which means that a data item which differs from an expected value appears at the data connection which is connected to the deactivated sense amplifier.

Abstract: An integrated semiconductor memory device includes a memory cell array with sense amplifiers that are combined in groups within the memory cell array. Each sense amplifier is associated with one data connection, the association varying on the basis of area within the memory cell array. When a memory cell is read, further adjacent memory cells besides the memory cell which is to be read are read, so that data are produced at all the data connections. To this end, the sense amplifiers in a group are activated together. To establish which sense amplifier within a group of sense amplifiers has a signaling connection to which data connection, individual sense amplifiers in a group can be deactivated specifically, which means that a data item which differs from an expected value appears at the data connection which is connected to the deactivated sense amplifier.

Abstract: In a configuration for checking an address generator, a memory apparatus is configured such that it can store values of address signals that are present on lines of an address bus. The stored values can then be output to at least one access point where the values are provided for further evaluation.

Abstract: For testing high-speed semiconductor memory devices (1) with a high data transfer rate, for instance DDR-DRAMs, controller modules (24) are provided in or as a constituent part of test receptacles (2) that are to be populated by a supply and handling system (3), said controller modules functionally essentially corresponding to customary graphic controllers. Components of the DRAMs (1) which determine the data transfer rate thereof are tested by means of the controller modules (24) at the supply and handling system (3), which is suitable for the high-volume throughout the DRAMs (1).

Abstract: For testing high-speed semiconductor memory devices with a high data transfer rate (such as DDR-DRAMs), in receiving units of supply and handling systems for tester apparatuses, selected graphic controllers are arranged on test assemblies, which are substantially structurally identical to graphics cards, and are connected via connecting lines to test receptacles for receiving the DRAMs. Components of the DRAMs that determine the data transfer rate thereof are tested by means of the graphic controllers at the supply and handling system.

Abstract: A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is described. The configuration has a delay locked loop (DLL) circuit for synchronizing an internal clock between a respective circuit and an external clock of the circuit system according to the phase difference between the two clocks in a manner dependent on phase changes in the signals. A response sensitivity of the DLL circuit is defined by a filter, which enables a renewed synchronization only after the arrival of a plurality of phase change events. The filter provided for setting the response sensitivity of the DLL circuit is of a variable configuration.

Abstract: In a configuration for checking an address generator, a memory apparatus is configured such that it can store values of address signals that are present on lines of an address bus. The stored values can then be output to at least one access point where the values are provided for further evaluation.

Abstract: The memory cells of a DRAM are refreshed such that the temporal sequence of the control signals for triggering the information refresh operation for the individual memory cells is set in accordance with the respective maximum retention time for the information in the memory cell.

Abstract: A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is described. The configuration has a delay locked loop (DLL) circuit for synchronizing an internal clock between a respective circuit and an external clock of the circuit system according to the phase difference between the two clocks in a manner dependent on phase changes in the signals. A response sensitivity of the DLL circuit is defined by a filter, which enables a renewed synchronization only after the arrival of a plurality of phase change events. The filter provided for setting the response sensitivity of the DLL circuit is of a variable configuration.

Abstract: The memory cells of a DRAM are refreshed such that the temporal sequence of the control signals for triggering the information refresh operation for the individual memory cells is set in accordance with the respective maximum retention time for the information in the memory cell.