Abstract: A test apparatus for generating reference scan chain test data comprises a test pattern generator and an output data modifier. The test pattern generator modifies a scan chain test input bit sequence by replacing a predefined number of start bits of the scan chain test input bit sequence by a predefined start bit sequence. Further, the test pattern generator provides the modified scan chain test input bit sequence to a device under test. The output data modifier modifies a scan chain test output bit sequence received from the device under test and caused by the modified scan chain test input bit sequence. The scan chain test output bit sequence is modified by replacing a predefined number of end bits of the scan chain test output bit sequence by a predefined end bit sequence to obtain the reference scan chain test data.

Abstract: A test apparatus for generating reference scan chain test data comprises a test pattern generator and an output data modifier. The test pattern generator modifies a scan chain test input bit sequence by replacing a predefined number of start bits of the scan chain test input bit sequence by a predefined start bit sequence. Further, the test pattern generator provides the modified scan chain test input bit sequence to a device under test. The output data modifier modifies a scan chain test output bit sequence received from the device under test and caused by the modified scan chain test input bit sequence. The scan chain test output bit sequence is modified by replacing a predefined number of end bits of the scan chain test output bit sequence by a predefined end bit sequence to obtain the reference scan chain test data.

Abstract: An apparatus for determining a number of successive equal bits preceding an edge within a bit stream including a repetitive bit sequence includes an edge number determiner, an edge selector, a time stamper and an equal bits determiner. The edge number determiner determines a preset number of edges. The preset number of edges is coprime to a number of edges of the repetitive bit sequence or coprime to a maximal number of edges of the repetitive bit sequence. The edge selector selects edges of the bit stream spaced apart from each other by the preset number of edges. Further, the time stamper determines a time stamp for each selected edge of the bit stream and the equal bits determiner determines the number of successive equal bits preceding the edge based on determined time stamps of selected edges.

Abstract: An apparatus for determining a number of successive equal bits preceding an edge within a bit stream including a repetitive bit sequence includes an edge number determiner, an edge selector, a time stamper and an equal bits determiner. The edge number determiner determines a preset number of edges. The preset number of edges is coprime to a number of edges of the repetitive bit sequence or coprime to a maximal number of edges of the repetitive bit sequence. The edge selector selects edges of the bit stream spaced apart from each other by the preset number of edges. Further, the time stamper determines a time stamp for each selected edge of the bit stream and the equal bits determiner determines the number of successive equal bits preceding the edge based on determined time stamps of selected edges.

Abstract: In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

Abstract: In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

Abstract: An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.

Abstract: An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include an indication of the failure-causing test data and the corresponding test analysis data. Embodiments are provided which enable that the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test, together with respective diagnosis data.

Abstract: An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.

Abstract: An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include an indication of the failure-causing test data and the corresponding test analysis data. Embodiments are provided which enable that the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test, together with respective diagnosis data.

Abstract: An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.

Abstract: Semiconductor devices including logic circuitry and embedded memories may be tested using one or more flip-flops in a scan chain that are connected to a control input of an MBIST logic, thereby allowing the control of the MBIST logic during a simultaneous scan test and memory test run. By combining the output of the MBIST logic with the output of the scan chain, fault diagnosis is maintained.

Abstract: An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.

Abstract: Semiconductor devices including logic circuitry and embedded memories may be more efficiently tested in that one or more flip-flops in a scan chain are connected to a control input of an MBIST logic, thereby allowing the control of the MBIST logic during a simultaneous scan test and memory test run. By combining the output of the MBIST logic with the output of the scan chain, fault diagnosis is maintained.