Abstract: A local oscillator signal generation circuit (150) for generating quadrature-related local oscillator signals comprises a source signal generator (153) arranged to generate a differential-mode source signal, a buffer stage (158) coupled to an output (156) of the source signal generator (153) and arranged to buffer the differential-mode source signal, and a quadrature generation stage (170) coupled to an output (168) of the buffer stage (158) and arranged to generate an in-phase local oscillator signal and a quadrature local oscillator signal from the buffered differential-mode source signal. The buffer stage (158) comprises a primary differential amplifier (159) having an input (162) coupled to an input (157) of the buffer stage (158), and a secondary differential amplifier (160) having an input (164) coupled to an output (163) of the primary differential amplifier (159) and an output (165) coupled to the output (168) of the buffer stage (158).

Abstract: An integrated circuit includes a clock generation stage that generates a clock signal having a clock frequency dependent on a reference signal. A delay stage generates a delayed clock signal by delaying the clock signal. A control stage generates a control signal indicative of a delay of the delayed clock signal relative to the clock signal. A frequency divider generates a divided signal by dividing a dividend signal having a dividend frequency dependent on the reference signal. A power supply regulator supplies power to the frequency divider at a first power level, which is dependent on the control signal.

Abstract: An integrated circuit (100) comprises a clock generation stage (120) arranged to generate a clock signal having a clock frequency dependent on a reference signal. A delay stage (130) is arranged to generate a Clock Generation Stage delayed clock signal by delaying the clock signal. A control stage (140) is arranged to generate a control signal indicative of a delay of the delayed clock signal relative to the clock signal. A frequency divider (150) arranged to generate a divided signal by dividing a dividend signal having a dividend frequency dependent on the reference signal. A power supply regulator (170) is arranged to supply power to the frequency divider (150) at a first power level, the first power level being dependent on the control signal.

Abstract: The invention relates to a circuit arrangement (4) for a PLL to be used in a terminal (50) of a time division cellular network. In a PLL according to the invention, the control voltage (32a) to a VCO (33) in the PLL is kept at a desired value also during time slots in which the terminal is not receiving or transmitting messages. The settling time for a PLL according to the invention is shot and the spurious effects caused by the power up thereof are small. The invention further relates to a method of operation for a PLL.

Abstract: The invention relates to a circuit arrangement (40) for a PLL to be used in a terminal (50) of a time-division cellular network. In a PLL according to the invention, the control voltage (32a) to a VCO (33) in the PLL is kept at a desired value also during time slots in which the terminal is not receiving or transmitting messages. The settling time for a PLL according to the invention is short and the spurious effects caused by the power-up thereof are small. The invention further relates to a method of operation for a PLL.