Abstract: First and second sets of numbers are received in an input range, which is separated into sub ranges. A first sub range is processed by initializing bits of a memory to a first logical state and by changing the initial state of each of the bits corresponding to a received number of the first set that is within the first sub range. Each number received in the second set is compared to a bit in the memory to identify a set of received numbers that are in the first sub range and that are in both the first set and the second set. The comparing is responsive to detecting a change of initial state of any bit in the memory during the processing of the first sub range. The processing and comparing is repeated for remaining sub ranges to identify received numbers that are in both the sets.

Abstract: The present invention relates to a computer program product, method and system for computing set intersection of a first and a second unordered set of discrete members that stem from a known input range of consecutive discrete numbers. The method breaks the numbers into subranges and for each subrange, utilizes a bit vector in a first random access memory, directly addressing bits representing values in a subrange in the first set to values in the second set in the subrange and writing each number of the second set that is also set member of the first set in the sub range directly to an output. This may be utilized by various applications including database applications. The algorithm may be offloaded to one or more processing subsystems.

Abstract: In consideration for the fact that a connection on the upper layers of an integrated circuit needs to access a lower layer to connect to, e.g., a transistor, at least one via on each layer is required below the top layer used by a connection for each pin. The vias (i.e., the connection structures between wiring planes within an integrated circuit) are arranged such that the number of wiring resources blocked on the lower layers is reduced. Various rules govern which vias are chosen. The main characteristic is to elect only a certain number of wiring channels appropriate for the vias on a single layer and then apply an optimization within the restricted elected wiring channels on that layer to select the most appropriate vias.

Abstract: In consideration for the fact that a connection on the upper layers of an integrated circuit needs to access a lower layer to connect to, e.g., a transistor, at least one via on each layer is required below the top layer used by a connection for each pin. The vias (i.e., the connection structures between wiring planes within an integrated circuit) are arranged such that the number of wiring resources blocked on the lower layers is reduced. Various rules govern which vias are chosen. The main characteristic is to elect only a certain number of wiring channels appropriate for the vias on a single layer and then apply an optimization within the restricted elected wiring channels on that layer to select the most appropriate vias.

Abstract: Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands.

Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.