Abstract: This disclosure relates to a transceiver element comprising receiving circuitry, down-converting circuitry, extracting circuitry and output circuitry. The receiving circuitry is configured to receive a radio frequency signal via an antenna element associated with the receiving circuitry. The radio frequency signal comprises a first received signal part and a second received signal part. The down-converting circuitry is configured to down-convert the radio frequency signal to provide a down-converted signal. The down-converted signal comprises a first down-converted signal part corresponding to the first received signal part and a second down-converted signal part corresponding to the second received signal part. The extracting circuitry is configured to extract at least the second down-converted signal part from the down-converted signal. The output circuitry is configured to provide an output signal comprising a first output signal part and a second output signal part.

Abstract: This disclosure relates to a transceiver element comprising receiving circuitry, down-converting circuitry, extracting circuitry and output circuitry. The receiving circuitry is configured to receive a radio frequency signal via an antenna element associated with the receiving circuitry. The radio frequency signal comprises a first received signal part and a second received signal part. The down-converting circuitry is configured to down-convert the radio frequency signal to provide a down-converted signal. The down-converted signal comprises a first down-converted signal part corresponding to the first received signal part and a second down-converted signal part corresponding to the second received signal part. The extracting circuitry is configured to extract at least the second down-converted signal part from the down-converted signal. The output circuitry is configured to provide an output signal comprising a first output signal part and a second output signal part.

Abstract: A MIMO transceiver has a plurality of analog processing subsystems that each includes at least one antenna, a duplexer, at least one power amplifier, at least one mixer, an interface connectable to a baseband processing subsystem, and the MIMO transceiver has one or more analog radio frequency processing chips. Each analog processing subsystem of the plurality of analog processing subsystems is on a single one of the analog radio frequency processing chips, and each analog radio frequency processing chip comprises a metallization on at least one side of the chip and wherein the metallization comprises integration of the at least one antenna.

Abstract: A MIMO transceiver has a plurality of analog processing subsystems that each includes at least one antenna, a duplexer, at least one power amplifier, at least one mixer, an interface connectable to a baseband processing subsystem, and the MIMO transceiver has one or more analog radio frequency processing chips. Each analog processing subsystem of the plurality of analog processing subsystems is on a single one of the analog radio frequency processing chips, and each analog radio frequency processing chip comprises a metallization on at least one side of the chip and wherein the metallization comprises integration of the at least one antenna.

Abstract: An analog processing subsystem is disclosed. Said subsystem comprising at least one antenna (202,302), a duplexer (202a,302a), at least one power amplifier (203a,203b), at least one mixer (204a,204b, 304a, 304b) and an interface connectable to a baseband processing subsystem. The at least one mixer (204a,204b,304a,304b) is adapted to down-convert and inphase/quadrature—IQ—demodulate a received analog radio frequency signal, received by the at least one antenna (202,302), to provide a received analog baseband signal and to IQ-modulate and up-convert a transmit analog baseband signal, to be transmitted by the at least one antenna (202, 302), to provide a transmit analog radio frequency signal. The analog processing subsystem is comprised on a single analog radio frequency processing chip (201,301) comprising a metallization on at least one side of the chip for integration of the at least one antenna (202,302).

Abstract: An analog processing subsystem is disclosed. Said subsystem comprising at least one antenna (202,302), a duplexer (202a,302a), at least one power amplifier (203a,203b), at least one mixer (204a,204b, 304a, 304b) and an interface connectable to a baseband processing subsystem. The at least one mixer (204a,204b,304a,304b) is adapted to down-convert and inphase/quadrature—IQ—demodulate a received analog radio frequency signal, received by the at least one antenna (202,302), to provide a received analog baseband signal and to IQ-modulate and up-convert a transmit analog baseband signal, to be transmitted by the at least one antenna (202, 302), to provide a transmit analog radio frequency signal. The analog processing subsystem is comprised on a single analog radio frequency processing chip (201,301) comprising a metallization on at least one side of the chip for integration of the at least one antenna (202,302).