Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer. The plurality of heat sink interconnects is located adjacent the high-power die in a horizontal direction.

Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer, where each of the plurality of heat sink interconnects is directly coupled to the heat transfer layer in a vertical orientation.

Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer, where each of the plurality of heat sink interconnects is directly coupled to the heat transfer layer in a vertical orientation.

Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer. The plurality of heat sink interconnects is located adjacent the high-power die in a horizontal direction.

Abstract: A device that includes a substrate; a die couple to the substrate, a frame located between the die and the substrate, wherein the frame is further located along a periphery of the die; a solder interconnect coupled to the frame and the substrate; and a sealed cavity located between the die and the substrate, wherein a wall of the sealed cavity is formed by the solder interconnect and the frame. The frame may be configured to be coupled to ground.

Abstract: Aspects of the disclosure are directed to wafer dicing with a frame. Accordingly, the dicing of the wafer includes forming a substrate layer in the wafer, wherein the substrate layer comprises a first substrate layer edge associated with the first device and a second substrate layer edge associated with the second device; depositing a passivation layer onto the substrate layer; and depositing a frame in the wafer, wherein the frame abuts the passivation layer and wherein the frame comprises a first frame edge associated with the first device and a second frame edge associated with the second device; and wherein a front width is a first distance between the first frame edge and the second frame edge, and a back width is a second distance between the first substrate layer edge and the second substrate layer edge; and wherein the front width is less than the back width.

Abstract: A device that includes a substrate, a first component coupled to the substrate, a second component coupled to the substrate, an encapsulation layer formed over the substrate such that the encapsulation layer encapsulates the first component and the second component, and a shielding layer formed over a first surface of the encapsulation layer. The shielding layer includes a first portion formed in a first cavity of the encapsulation layer. The first cavity is located between the first component and the second component. The first portion of the shielding layer provides a compartmental electromagnetic (EM) shield between the first component and the second component.