Abstract: A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.

Abstract: The present invention relates to a method of coupling at least one (conventional) unit processing data in a sequential manner, e.g. a CPU, von-Neumann-Processor and/or microcontroller, the (conventional) unit for data processing comprising an instruction pipeline, and an array for processing data comprising a plurality of data processing cells, e.g. a preferably coarse grain and/or preferably runtime reconfigurable data processor, FPGA, DFP, DSP, XPP or chaemeleon-technology-like data processing fabric, wherein the array is coupled to the instruction pipeline.

Abstract: In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Abstract: A method for partitioning large computer programs and or algorithms at least part of which is to be executed by an array of reconfigurable units such as ALUS, comprising the steps of defining a maximum allowable size to be mapped onto the array, partitioning the program such that its separate parts minimize the overall execution time and providing a mapping onto the array not exceeding the maximum allowable size is described.

Abstract: A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.

Abstract: The invention relates to a method for compiling programs on a system consisting of at least one first processor and a reconfigurable unit. It is provided in this method that the code parts suitable for the reconfigurable unit are determined and extracted and the remaining code is extracted in such a manner for processing by the first processor.