Abstract: A system including circuitry to communicate data across an isolation barrier of a switch driver circuit. For switch driver circuits with galvanic isolation, the circuitry of this disclosure uses the unavoidable common mode voltages caused by the coupling capacitances of the data transfer circuit to evaluate the common mode voltage characteristics, such as the slew rate of a switching event. The switch driver circuit of this disclosure may include a common mode voltage detector to detect and measure features of the unavoidable common mode voltage during a switching event, such as voltage amplitude and slew rate. The common mode voltage detector may couple to a communication interface that provides the common mode voltage information to a controller for the switch driver circuit. In some examples, based on the received information, the controller may adjust the operation of the switching circuit.

Abstract: A driver circuit controls a half-bridge that includes a high-side power switch and a low-side power switch. The driver circuit may comprise a high-side compare unit configured to determine a first drain-to-source voltage, wherein the first drain-to-source voltage is associated with the high-side power switch when the high-side power switch is ON, and a low-side compare unit configured to determine a second drain-to-source voltage, wherein the second drain-to-source voltage is associated with the low-side power switch when the low-side power switch is ON. The high-side compare unit may be further configured to determine a third drain-to-source voltage, wherein the third drain-to-source voltage is associated with the high-side power switch when the high-side power switch is OFF, and the low-side compare unit may be further configured to determine a fourth drain-to-source voltage, wherein the fourth drain-to-source voltage is associated with the low-side power switch when the low-side power switch is OFF.

Abstract: A driver circuit controls a half-bridge that includes a high-side power switch and a low-side power switch. The driver circuit may comprise a high-side compare unit configured to determine a first drain-to-source voltage, wherein the first drain-to-source voltage is associated with the high-side power switch when the high-side power switch is ON, and a low-side compare unit configured to determine a second drain-to-source voltage, wherein the second drain-to-source voltage is associated with the low-side power switch when the low-side power switch is ON. The high-side compare unit may be further configured to determine a third drain-to-source voltage, wherein the third drain-to-source voltage is associated with the high-side power switch when the high-side power switch is OFF, and the low-side compare unit may be further configured to determine a fourth drain-to-source voltage, wherein the fourth drain-to-source voltage is associated with the low-side power switch when the low-side power switch is OFF.

Abstract: A driver circuit may be configured to control a power switch. The driver circuit may comprise an output pin configured to deliver signals to a gate of the power switch to control an ON/OFF state of the power switch, and a comparator configured to compare a gate-to-source voltage of the power switch to a first threshold when the power switch is ON and to compare the gate-to-source voltage of the power switch to a second threshold when the power switch is OFF.

Abstract: In accordance with an embodiment, a method includes driving a predetermined load using a driver circuit according to a drive pattern; supplying power to the driver circuit using a switched-mode power supply (SMPS) configured to be coupled to at least one external component; and verifying functionality of the SMPS while driving the predetermined load. Verifying the functionality includes monitoring at least one operating parameter of the SMPS, where the at least one operating parameter of the SMPS is dependent on the drive pattern and the at least one external component, comparing the at least one operating parameter to at least one expected operating parameter to form a first comparison result, and indicating an error condition based on the first comparison result.

Abstract: In accordance with an embodiment, a method includes using a monitoring circuit disposed on a monolithic integrated circuit to monitor an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit; using a time measuring circuit disposed on the monolithic integrated circuit to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, where the first drive signal is configured to cause a change of state of the first switching transistor; using an analysis circuit disposed on the monolithic integrated circuit to compare the measured first time delay with a first predetermined threshold to form a first comparison result; and indicating a first error condition based on the first comparison result.

Abstract: In accordance with an embodiment, a method includes monitoring a first voltage across a buffer capacitor; activating a first current path between a power supply node and the buffer capacitor when the monitored first voltage is below a first threshold voltage, activating a second current path between the power supply node and the buffer capacitor when the monitored first voltage is below a second threshold voltage, and transferring power from the buffer capacitor to a driver circuit coupled across the buffer capacitor.

Abstract: A driver circuit associated with a power electronic system is disclosed. The driver circuit comprises a gate driver circuit configured to drive a switching circuit comprising a plurality of switches in parallel, each switch comprising a respective source bondwire. The driver circuit further comprises a bondwire fault detection circuit comprising a gate charge estimation circuit configured to measure a parameter of the switching circuit comprising a gate charge of the switching circuit or a parameter indicative of the gate charge associated with the switching circuit. The bondwire fault detection circuit further comprises a detection circuit configured to detect a fault associated with at least one source bondwire of the switching circuit, based on the measured parameter of the switching circuit.

Abstract: In accordance with an embodiment, a method includes using a monitoring circuit disposed on a monolithic integrated circuit to monitor an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit; using a time measuring circuit disposed on the monolithic integrated circuit to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, where the first drive signal is configured to cause a change of state of the first switching transistor; using an analysis circuit disposed on the monolithic integrated circuit to compare the measured first time delay with a first predetermined threshold to form a first comparison result; and indicating a first error condition based on the first comparison result.

Abstract: A method includes applying a current to an input pin of an integrated circuit; converting an analog signal at the input pin to a digital stream using a Sigma-Delta modulator; converting the digital stream to a first digital output signal proportional to the analog signal in a first input range between a first analog signal value and a second analog signal value, where the first input range corresponds to a pre-determined range of the analog signal smaller than a full-scale input range of the analog signal; converting the digital stream to a second output signal; comparing the second output signal to a first threshold corresponding to a third analog signal value at the input pin that is outside of the first input range; and providing an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.

Abstract: A driver circuit associated with a power electronic system is disclosed. The driver circuit comprises a gate driver circuit configured to drive a switching circuit comprising a plurality of switches in parallel, each switch comprising a respective source bondwire. The driver circuit further comprises a bondwire fault detection circuit comprising a gate charge estimation circuit configured to measure a parameter of the switching circuit comprising a gate charge of the switching circuit or a parameter indicative of the gate charge associated with the switching circuit. The bondwire fault detection circuit further comprises a detection circuit configured to detect a fault associated with at least one source bondwire of the switching circuit, based on the measured parameter of the switching circuit.

Abstract: A method of monitoring a gate of a transistor includes monitoring a gate voltage of the transistor; measuring a first time difference between when a gate control signal is asserted and when the gate voltage of the transistor crosses a first voltage threshold based on the monitoring; measuring a second time difference between when the gate voltage of the transistor crosses the first voltage threshold and when the gate voltage of the transistor crosses a second voltage threshold based on the monitoring; and determining whether the first time difference falls within a first time window, and whether the second time difference falls within a second time window.

Abstract: Disclosed is an electronic drive circuit and a drive method. The drive circuit includes an output; a first output transistor comprising a control node and a load path, wherein the load path is coupled between the output and a first supply node; a voltage regulator configured to control a voltage across the load path of the first output transistor; and a first driver configured to drive the first output transistor based on a first control signal.

Abstract: One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.

Abstract: An integrated circuit arrangement (100, 200, 600) has a first circuit part (102, 202, 602) which can be supplied with a first supply voltage (106, 206, 606), and a second circuit part (104, 204, 604) which can be supplied with a second supply voltage (108, 208, 608). The first circuit part and the second circuit part are arranged in a manner spatially separate from one another. The first circuit part has a first conduction element (110, 210, 310, 410, 610), and the second circuit part has a second conduction element (112, 212, 312, 412, 612). The integrated circuit arrangement also has a third conduction element (114, 214, 314, 414, 614), the third conduction element being arranged between the first conduction element and the second conduction element in such a manner that the third conduction element is arranged adjacent to the first conduction element and the third conduction element is also arranged adjacent to the second conduction element.

Abstract: Disclosed is an electronic drive circuit and a drive method. The drive circuit includes an output; a first output transistor comprising a control node and a load path, wherein the load path is coupled between the output and a first supply node; a voltage regulator configured to control a voltage across the load path of the first output transistor; and a first driver configured to drive the first output transistor based on a first control signal.

Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes performing a test during the forming of the semiconductor device within and/or over a substrate. A first voltage is applied to a first node coupled to a component to be tested in the substrate and a test voltage at a pad coupled to the component to be tested through a second node. The test voltage has a peak voltage higher than the first voltage. The component to be tested is coupled between the first node and the second node. A leakage current is measured through the component to be tested in response to the test voltage. After performing the test, the second node is connected to a functional block in the substrate. The first node is coupled to a third node coupled to the functional block.

Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes performing a test during the forming of the semiconductor device within and/or over a substrate. A first voltage is applied to a first node coupled to a component to be tested in the substrate and a test voltage at a pad coupled to the component to be tested through a second node. The test voltage has a peak voltage higher than the first voltage. The component to be tested is coupled between the first node and the second node. A leakage current is measured through the component to be tested in response to the test voltage. After performing the test, the second node is connected to a functional block in the substrate. The first node is coupled to a third node coupled to the functional block.

Abstract: An integrated circuit arrangement (100, 200, 600) has a first circuit part (102, 202, 602) which can be supplied with a first supply voltage (106, 206, 606), and a second circuit part (104, 204, 604) which can be supplied with a second supply voltage (108, 208, 608). The first circuit part and the second circuit part are arranged in a manner spatially separate from one another. The first circuit part has a first conduction element (110, 210, 310, 410, 610), and the second circuit part has a second conduction element (112, 212, 312, 412, 612). The integrated circuit arrangement also has a third conduction element (114, 214, 314, 414, 614), the third conduction element being arranged between the first conduction element and the second conduction element in such a manner that the third conduction element is arranged adjacent to the first conduction element and the third conduction element is also arranged adjacent to the second conduction element.

Abstract: One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.