Abstract: A decoupling capacitor is disclosed that has an n-type portion and a p-type portion in a semiconductor. The decoupling capacitor is formed of an NFET transistor and a PFET transistor, the PFET transistor being substantially formed in the n-type portion and the NFET transistor being substantially formed in the p-type portion, a boundary between the n-type portion and the p-type portion being substantially straight. The transistors are arranged such that a source and drain of the PFET transistor are connected to a high voltage rail and a source and drain of the NFET transistor are connected to a low voltage rail.

Abstract: The application discloses a circuit comprising at least one flip flop, said flip flop comprising: a master latch and a slave latch; a data signal input and a scan signal input arranged in parallel to each other and each input comprising a tristateable device; and a scan enable signal input, a functional clock signal input and a scan clock signal input; wherein: in response to a first predetermined value of said scan enable signal indicating a functional mode of operation, said scan input tristateable device is operable to isolate said scan input from said master latch, and said master latch is operable in response to said functional clock to receive data from said data input and to output data to said slave latch and said slave latch is operable in response to said functional clock to receive data from said master latch and to output data at said data output; and in response to a second predetermined value of said scan enable signal indicating a scan mode of operation said data input tristateable device is op

Abstract: The application discloses a semiconductor memory storage device comprising: a data retention portion comprising latches; a peripheral portion comprising read and write logic; and a power switching device wherein said peripheral portion is operable to be powered by a periphery voltage difference; said data retention portion is operable to be powered by a data retention voltage difference said data retention voltage difference being different to said periphery voltage difference; and in response to a write request signal to write to at least one of said latches output from said peripheral portion to said data retention portion by said write logic, said power switching device is operable to reduce a voltage difference across said at least one of said latches such that a data signal output from said peripheral portion and having a voltage level determined by said periphery voltage difference is able to write to said at least one of said latches.

Abstract: The application discloses a semiconductor memory storage device comprising: a data retention portion comprising latches; a peripheral portion comprising read and write logic; and a power switching device wherein said peripheral portion is operable to be powered by a periphery voltage difference; said data retention portion is operable to be powered by a data retention voltage difference said data retention voltage difference being different to said periphery voltage difference; and in response to a write request signal to write to at least one of said latches output from said peripheral portion to said data retention portion by said write logic, said power switching device is operable to reduce a voltage difference across said at least one of said latches such that a data signal output from said peripheral portion and having a voltage level determined by said periphery voltage difference is able to write to said at least one of said latches.

Abstract: A clocked scan flip-flop 2 is provided in which a latch 14 within the diagnostic data path is reused to store an operational signal value during a sleep mode. The operational signal value is supplied to the latch 14 via a sleep mode path 20 through a transmission gate 22 (or other tristate driver) controlled by a sleep mode control signal SLP. The diagnostic clock signal SCLK, the operational clock signal CLK and the sleep mode control signal SLP together provide the control operations for controlling the various elements within the clocked-scan flip-flop 2 to move into and out of sleep mode.

Abstract: A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a tristateable device, said tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said second sleep signal being rece

Abstract: A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a bidirectional tristateable device, said bidirectional tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said se

Abstract: The application relates to a circuit for storing a signal during sleep mode, said embodiments of the circuit comprising: a sleep signal input operable to receive a sleep signal; a clock signal input operable to receive a clock signal; a plurality of latches clocked by said clock signal, at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of at least one of said plurality of latches, said at least one tristateable device being operable to selectively isolate said input of said at least one latch in response to a predetermined clock signal value; clock signal distribution means operable to distribute said clock signal to said plurality of latches and said at least one tristateable device; wherein in response to a sleep signal said circuit is operable to: reduce a voltage difference across at least a portion of said circuit such that said portion of said circuit is powered down; and maintain a voltage difference across at least one stora

Abstract: The application relates to a circuit for storing a signal during sleep mode, said embodiments of the circuit comprising: a sleep signal input operable to receive a sleep signal; a clock signal input operable to receive a clock signal; a plurality of latches clocked by said clock signal, at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of at least one of said plurality of latches, said at least one tristateable device being operable to selectively isolate said input of said at least one latch in response to a predetermined clock signal value; clock signal distribution means operable to distribute said clock signal to said plurality of latches and said at least one tristateable device; wherein in response to a sleep signal said circuit is operable to: reduce a voltage difference across at least a portion of said circuit such that said portion of said circuit is powered down; and maintain a voltage difference across at least one stora

Abstract: The application relates to a circuit for storing a signal during sleep mode, said embodiments of the circuit comprising: a sleep signal input operable to receive a sleep signal; a clock signal input operable to receive a clock signal; a plurality of latches clocked by said clock signal, at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of at least one of said plurality of latches, said at least one tristateable device being operable to selectively isolate said input of said at least one latch in response to a predetermined clock signal value; clock signal distribution means operable to distribute said clock signal to said plurality of latches and said at least one tristateable device; wherein in response to a sleep signal said circuit is operable to: reduce a voltage difference across at least a portion of said circuit such that said portion of said circuit is powered down; and maintain a voltage difference across at least one stora

Abstract: A clocked scan flip-flop 2 is provided in which a latch 14 within the diagnostic data path is reused to store an operational signal value during a sleep mode. The operational signal value is supplied to the latch 14 via a sleep mode path 20 through a transmission gate 22 (or other tristate driver) controlled by a sleep mode control signal SLP. The diagnostic clock signal SCLK, the operational clock signal CLK and the sleep mode control signal SLP together provide the control operations for controlling the various elements within the clocked-scan flip-flop 2 to move into and out of sleep mode.

Abstract: A circuit 2 for storing a signal value includes an operational data path formed by an operational path latch 4 and a shared latch 6. A diagnostic data path is formed by a diagnostic path latch 12 and the shared latch 6. An operational clock signal CLK controls the operational path and a diagnostic clock signal SCLK controls the diagnostic path. When the operational clock signal CLK is active in the operational mode, the diagnostic clock signal SCLK is held at a predetermined value to disable the diagnostic data path and enable action of the shared latch as part of the operational data path. Conversely, in the diagnostic mode, the diagnostic clock signal SCLK is active and the operational clock signal CLK is held at a predetermined value to disable the operational data path and enable the shared latch 6 as part of the diagnostic data path.