Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.

Abstract: A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the integrated circuit, providing compatibility information indicative of the compatibility of the boundaries of the standard cells, and generating a placement of standard cells in dependence on the functional data and the compatibility information to produce the layout such that no abutting cells have incompatible boundaries.

Abstract: A technique for generating a layout of an integrated circuit places standard cells in position and provides power rail conductors formed in a second metal layer overlying power connection conductors formed in a first metal layer via which the power is supplied to the standard cells. Routing connection conductors are added in the first metal layer and are permitted to pass through gaps between the power connection conductors of the first metal layer and underneath the power rail conductors of the second metal layer. Once routing has been performed, gaps between the power connection conductors of the first metal layer underlying the power rail conductors and not being used by routing connection conductors are closed so as form interrupted power rail conductors within the first meal layer.

Abstract: A method of design of a standard cell and a standard cell is disclosed. The method design comprising the steps of: identifying a non-uniformity in a boundary condition of said standard cell that would affect a characteristic of a neighbouring standard cell; introducing a further non-uniformity into said cell to mitigate the effect of said identified non-uniform boundary condition on said characteristic of said neighbouring standard cell.

Abstract: A layout for an integrated circuit includes standard cells positioned at standard cell sites. Programmable cells are positioned at programmable fill sites which have a size sufficient to accommodate the programmable cells and are not occupied by standard cells. The position of these programmable sites is recorded in site data as part of the layout data associated with the layout. Empty standard cell sites remaining after standard cells and programmable cells have been placed are filled with standard fill cells. The boundaries of the programmable cells are not constrained other than by alignment with standard cell sites. This permits a high density of programmable fill sites and programmable cells to be achieved. When it is desired to replace a programmable cell with a programmed cell the programmable cells are all deleted from the layout and then the required programmed cells are subject to an automated placement algorithm to place them where appropriate for their function.

Abstract: A circuit 32 is provided comprising a first diffusion region 34 and a parallel second diffusion region 36. A sequence of N gate layers 40, 42, 46 is provided with a first and an Nth of these gate layers covering different respective ones of the diffusion regions 34, 36 whilst the middle (N?2) gate layers 42 cover both diffusion regions 34, 36. A bridging conductor 64 connects the first gate layer 40 and the Nth gate layer 46. In some embodiments, the second diffusion region is provided as two second diffusion sub-regions 68, 70 having a diffusion region gap 74 therebetween and electrically connected via a jumper connector 42. A first gate layer 76 which forms a gate electrode with a first diffusion region 66 can extend through this diffusion region gap 74 not forming a gate electrode therewith and facilitating use of a collinear bridging conductor 82 to connect to the Nth gate layer 80.

Abstract: State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 12 is controlled by a first clock signal nclk and a second clock signal bclk. The tristate inverter circuitry 2 is controlled by a third clock signal nfclk and a fourth clock signal flck. The clock generating circuitry holds the third and fourth clock signals at fixed values which tristate the tristate inverter circuitry 2 when in scan mode. This moves scan control logic out of the function path comprising the tristate inverter circuitry into the clock control circuitry.

Abstract: A method of forming an integrated circuit 68 provides over a diffusion region 28 on a substrate 26 a gate electrode 36. A source electrode is provided by a source local interconnect conductor 30 and a drain electrode is provided by a drain local interconnect conductor 32. An insulator layer 38 is formed over these electrodes and respective electrode openings are formed through the insulator layer 38 so as to provide electrical connection to a Metal1 layer 46, 48, 50. The etching process for the electrode openings is controlled such that the maximum etching depth is insufficient to penetrate through the insulating layer 38 and accordingly short circuit a gate insulator layer 34 provided between the diffusion region 28 and the gate electrode 36. Thus, the gate opening may be positioned over the diffusion region 28.

Abstract: A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the integrated circuit, providing compatibility information indicative of the compatibility of the boundaries of the standard cells, and generating a placement of standard cells in dependence on the functional data and the compatibility information to produce the layout such that no abutting cells have incompatible boundaries.

Abstract: A layout for an integrated circuit includes standard cells 6 positioned at standard cell sites 4. Programmable cells 10 are positioned at programmable fill sites 8 which have a size sufficient to accommodate the programmable cells 10 and are not occupied by standard cells 6. The position of these programmable sites 8 is recorded in site data as part of the layout data associated with the layout 2. Empty standard cell sites 4 remaining after standard cells 6 and programmable cells 10 have been placed are filled with standard fill cells 12. The boundaries of the programmable cells 10 are not constrained other than by alignment with standard cell sites 4. This permits a high density of programmable fill sites 8 and programmable cells 10 to be achieved.

Abstract: A circuit 32 is provided comprising a first diffusion region 34 and a parallel second diffusion region 36. A sequence of N gate layers 40, 42, 46 is provided with a first and an Nth of these gate layers covering different respective ones of the diffusion regions 34, 36 whilst the middle (N-2) gate layers 42 cover both diffusion regions 34, 36. A bridging conductor 64 connects the first gate layer 40 and the Nth gate layer 46. In some embodiments, the second diffusion region is provided as two second diffusion sub-regions 68, 70 having a diffusion region gap 74 therebetween and electrically connected via a jumper connector 42. A first gate layer 76 which forms a gate electrode with a first diffusion region 66 can extend through this diffusion region gap 74 not forming a gate electrode therewith and facilitating use of a collinear bridging conductor 82 to connect to the Nth gate layer 80.

Abstract: A technique for generating the layout of an integrated circuit 2 places the standard cells 8, 10, 12 in position and provides power rail conductors 38, 40, 42 formed in a second metal layer overlying power connection conductors 14 to 30 formed in a first metal layer via which the power is supplied to the standard cells. Routing connection conductors 32, 34, 36 are added in the first metal layer and are permitted to pass through gaps between the power connection conductors of the first metal layer and underneath the power rail conductors of the second metal layer. Once routing has been performed, gaps between the power connection conductors of the first metal layer underlying the power rail conductors and not being used by routing connection conductors are closed so as form interrupted power rail conductors within the first meal layer.

Abstract: A method of design of a standard cell and a standard cell is disclosed. The method design comprising the steps of: identifying a non-uniformity in a boundary condition of said standard cell that would affect a characteristic of a neighbouring standard cell; introducing a further non-uniformity into said cell to mitigate the effect of said identified non-uniform boundary condition on said characteristic of said neighbouring standard cell.

Abstract: The application discloses state storage circuitry comprising: an operational data input for receiving input data, a diagnostic data input for receiving diagnostic data and a diagnostic select signal input; a storage element for storing a value indicative of data received from one of said operational data input and said diagnostic data input; an output for outputting said value stored in said storage element; a pulse generator for generating pulses in response to a clock signal, said pulse generator comprising a diagnostic output and a functional output and being responsive to receipt of a diagnostic enable signal at said diagnostic select signal input to output said generated pulses at said diagnostic output and being responsive to receipt of a diagnostic disable signal at said diagnostic select signal input to output said generated pulses at said functional output; an operational path switch for receiving said pulses from said functional output and being responsive to receipt of each of said pulses to provid

Abstract: State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 12 is controlled by a first clock signal nclk and a second clock signal bclk. The tristate inverter circuitry 2 is controlled by a third clock signal nfclk and a fourth clock signal flck. The clock generating circuitry holds the third and fourth clock signals at fixed values which tristate the tristate inverter circuitry 2 when in scan mode. This moves scan control logic out of the function path comprising the tristate inverter circuitry into the clock control circuitry.

Abstract: A method of forming an integrated circuit 68 provides over a diffusion region 28 on a substrate 26 a gate electrode 36. A source electrode is provided by a source local interconnect conductor 30 and a drain electrode is provided by a drain local interconnect conductor 32. An insulator layer 38 is formed over these electrodes and respective electrode openings are formed through the insulator layer 38 so as to provide electrical connection to a Metal1 layer 46, 48, 50. The etching process for the electrode openings is controlled such that the maximum etching depth is insufficient to penetrate through the insulating layer 38 and accordingly short circuit a gate insulator layer 34 provided between the diffusion region 28 and the gate electrode 36. Thus, the gate opening may be positioned over the diffusion region 28.