Patents by Inventor Marlon Basa Verdan

Marlon Basa Verdan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scatter-gather approach for parallel data transfer in a mass storage system
    Patent number: 10489318
    Abstract: In an embodiment of the invention, an apparatus comprises: a first flash module comprising a first flash device; and a second flash module comprising a second flash device; wherein the first flash module and second flash module are coupled by a flash interconnect; wherein the first flash device is configured to store a first data stripe of a data and wherein the second flash device is configured to store a second data stripe of the data. In another embodiment of the invention, a method comprises: storing, in a first flash device in a first flash module, a first data stripe of a data; and storing, in a second flash device in a second flash module, a second data stripe of the data; wherein the first flash module and second flash module are coupled by a flash interconnect.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: November 26, 2019
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Ricardo H. Bruce, Avnher Villar Santos, Marlon Basa Verdan, Elsbeth Lauren Tagayo Villapana
  • Bus arbitration with routing and failover mechanism
    Patent number: 10430303
    Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 1, 2019
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Ricardo H. Bruce, Cyrill Coronel Ponce, Jarmie Dela Cruz Espuerta, Marlon Basa Verdan
  • Scatter-gather approach for parallel data transfer in a mass storage system
    Patent number: 9971524
    Abstract: An embodiment of the invention provides a method for optimizing flash device accesses, comprising: interleaving and striping, in tandem, for a transfer of data the other portions of the data.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: May 15, 2018
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Ricardo H. Bruce, Avnher Villar Santos, Marlon Basa Verdan, Elsbeth Lauren Tagayo Villapana
  • Bus arbitration with routing and failover mechanism
    Patent number: 9916213
    Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: March 13, 2018
    Assignee: BITMICRO Networks, Inc.
    Inventors: Ricardo H. Bruce, Cyrill Coronel Ponce, Jarmie De La Cruz Espuerta, Marlon Basa Verdan
  • Network of memory systems
    Patent number: 9875205
    Abstract: A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: January 23, 2018
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Ricardo H. Bruce, Jarmie De La Cruz Espuerta, Marlon Basa Verdan