Patents by Inventor Marni Nabors

Marni Nabors has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200279069
    Abstract: An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.
    Type: Application
    Filed: December 28, 2017
    Publication date: September 3, 2020
    Inventors: Ranjith KUMAR, Mark T. BOHR, Ruth A. BRAIN, Marni NABORS, Tai-Hsuan WU, Sourav CHAKRAVARTY
  • Publication number: 20200251464
    Abstract: An integrated circuit structure includes a cell on a metal level, the cell defined by a cell boundary. A plurality of substantially parallel interconnect lines are inside the cell boundary. A first power track and a second power track are both dedicated to power and are located completely inside the cell boundary without any power tracks along the cell boundary on the metal level.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Inventors: Srinivasa Chaitanya GADIGATLA, Ranjith KUMAR, Marni NABORS, Quan PHAN
  • Publication number: 20190378836
    Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Inventors: Yih WANG, Rishabh MEHANDRU, Mauro J. KOBRINSKY, Tahir GHANI, Mark BOHR, Marni NABORS
  • Publication number: 20190378790
    Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Applicant: Intel Corporation
    Inventors: Mark Bohr, Mauro Kobrinsky, Marni Nabors