Abstract: Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.

Abstract: The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to top of stack including a push or pop.

Abstract: The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to, top of stack including a push or pop.

Abstract: Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.

Abstract: Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are being read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.

Abstract: The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to top of stack including a push or pop.

Abstract: The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to top of stack including a push or pop.

Abstract: In an instruction a relative jump distance is expressed as a number of instructions rather than as a number of addresses. Instructions have various lengths. After encountering the instruction the processing device loads the following instructions but suppresses execution of a set of instructions that consists of the number of instructions expressed in the relative jump instruction.

Abstract: A data processing system with a look-up table means for implementing a transfer function with non-uniform resolution comprises a memory to store a plurality of function data; an input to receive external address words for operating on the memory; and an output to provide the function data. The look-up table means comprises a converging means between the input and the memory for mapping specific ones of the external address words onto a specific one of internal address words to access the memory. This greatly reduces memory size. If the transfer function has a symmetry property, a symmetry-handling means further reduces the memory size.

Abstract: An audio system has an attacher station for attaching to and decoding an audio representation channel, which also has a first auxiliary information sub-channel. A user station is fed by the attacher station through a unidirectional interface and receives the auxiliary information in an application context under control of a user interface for selective displaying. The attacher station extracts the auxiliary information from the channel. The system also has a framework data generator that is instantiatable by information from the information sub-channel, and a framework packetizer fed by the generator for supplementing the audio representation channel on said unidirectional interface in a second auxiliary information sub-channel by packetized and instantiated application information for the user station.

Abstract: A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output. The system includes a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus including a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit.

Abstract: A communication system has multiple and uniformly weighted station interconnected by a shared digital bus. A particular station comprises globally relevant information, and, with a predetermined maximum recurrence time, transmits a data packet representing such item to any other interested station. If unanimous counter signalization occurs, the item is in order, other wise updating thereof is undertaken. The unanimity is either by positive signalization, or by default.

Abstract: The apparatus includes first, second and third connectors, a control signal generator (5.11) and first and second switches (5.9, 5.10). The first and second connectors each have a signal input terminal, a signal output terminal and a control signal terminal. The third connector has a signal input terminal (5.7) and eventually a control signal terminal (5.8). The first and second switching means each have first (a), second (b) and third (c) terminals, the first terminal (a) of the first switches (5.9) being coupled to the signal output terminal (5.5) of the second connector, the second terminal (b) of the first switches (5.9) being coupled to the signal input terminal (5.1) of the first connector, the first terminal (a) of the second switching means (5.10) being coupled to the signal output terminal (5.2) of the first connector, the second terminal (b) of the second switching means (5.10) being coupled to the signal input terminal (5.4) of the second connector. The first and second switches (5.9, 5.

Abstract: The apparatus includes first, second and third connectors, a control signal generator (5.11) and first and second switches (5.9, 5.10). The first and second connector each have a signal input terminal, a signal output terminal and a control signal terminal. The third connector has a signal input terminal (5.7) and eventually a control signal terminal (5.8). The first and second switches each have first (a), second (b) and third (c) terminals, the first terminal (a) of the first switches (5.9) being coupled to the signal output terminal (5.5) of the second connector, the second terminal (b) of the first switches (5.9) being coupled to the signal input terminal (5.1) of the first connector, the first terminal (a) of the second switches (5.10) being coupled to the signal output terminal (5.2) of the first connector, the second terminal (b) of the second switches (5.10) being coupled to the signal input terminal (5.4) of the second connector. The first and second switches (5.9, 5.