Patents by Inventor Marokkey Raphael Sajan

Marokkey Raphael Sajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6355399
    Abstract: A new method is provided for the creation of a dual damascene structure. The method of the invention uses a gray tone mask to form dual damascene trenches in one single masking and etch step. The gray tone mask technology allows for a photoresist patterning process after which the photoresist profile can be transferred into the underlying substrate by an etch process. By making the photoresist profile equal to the profile of a dual damascene structure, the dual damascene profile can be created in the surface of a substrate.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: March 12, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Marokkey Raphael Sajan, Zhu Sui Hua, Tsun-Lung Alex Cheng
  • Patent number: 6248484
    Abstract: Hybrid alignment markings with a plurality of parallel marks on an active area of a silicon layer on which a multilayer structure are formed by forming initial marks in the active area by modifying the profile of the active area producing an active area surface of the active area with initial marks and then forming on the active area surface a set of interleaved marks from a second, polysilicon layer to form a single composite alignment marking composed of the initial marks and the interleaved marks. One technique is to form shallow steps with shallow trenches with low mesas in the silicon layer followed by forming low ribs of the second, polysilicon layer on the low mesas adjacent interleaved with the shallow trenches. Alternatively, form shallow cavities with low ribs in the silicon layer forming exposed low cavity surfaces of the silicon layer, and then form additional low ribs of a polysilicon layer in the shallow cavities on the exposed low cavity surfaces of the silicon layer.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: June 19, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Marokkey Raphael Sajan, Alex (Tsun-Lung) Cheng
  • Patent number: 6242344
    Abstract: Under the first embodiment of the invention, a three layer composite layer of insulation is deposited. The trench is etched into this composite layer of insulation followed by a hard bake. The via etch is performed, completing the formation of the dual damascene profile. The created dual damascene profile is transferred into the underlying substrate; the layer of photoresist is removed. Under the second embodiment of the invention, a two layer composite layer of insulation is deposited over a semiconductor surface. The trench is etched into this composite layer of insulation. A layer of positive photoresist is deposited over the second layer of cross-linked negative resist and masked for the via etch. The via etch is performed, the created dual damascene profile is transferred into the underlying substrate. The removal of the layers of patterned photoresist completes the formation of the dual damascene structure.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: June 5, 2001
    Assignee: Institute of Microelectronics
    Inventors: Leong Tee Koh, Marokkey Raphael Sajan, Tsun-Lung Alex Cheng, Joseph Zhifeng Xie