Patents by Inventor Mars Chen

Mars Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single-transistor EEPROM array and operation methods
    Patent number: 8300462
    Abstract: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 30, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen
  • Single-Transistor EEPROM Array and Operation Methods
    Publication number: 20120134209
    Abstract: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen
  • Single-transistor EEPROM array and operation methods
    Patent number: 8120956
    Abstract: An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: February 21, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen
  • Single-Transistor EEPROM Array and Operation Methods
    Publication number: 20100290284
    Abstract: An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.
    Type: Application
    Filed: February 19, 2010
    Publication date: November 18, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen