Abstract: A digital logic buffer device for generating dual polarity analog signals is described. In the presently preferred embodiment, buffer receives the positive polarity analog output of a digital-to-analog converter (V.sub.DAC), and a sign bit. If the sign bit indicates that a positive polarity is required, the buffer will output approximately V.sub.DAC. If a negative polarity is required, aproximately -V.sub.DAC will be generated.

Abstract: An integrated circuit processor real time processing of analog signals is described. The programmable processor duplicates filters, waveform generators and non-linear functions, such as rectification, with a high degree of stability and at a relatively low cost. A two-port, random-access memory provides inputs to an arithmetic logic unit (ALU). One of these inputs is coupled through a scaler (shifter). This scaler in conjunction with the ALU provides efficient multiplication, particularly by coefficients. ALU overflows are handled in an unusual manner to eliminate additional processing time for overflows. In a typical application, the one chip processor, with its 192-word program, samples an input analog signal at the rate of 13,020 Hz and detects the 8 tones used in telephony.