Patents by Inventor Marshall D. Tiner
Marshall D. Tiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10892743Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: February 25, 2019Date of Patent: January 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20190190506Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: February 25, 2019Publication date: June 20, 2019Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 10291217Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: March 13, 2017Date of Patent: May 14, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 10156882Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.Type: GrantFiled: October 9, 2015Date of Patent: December 18, 2018Assignee: International Business Machines CorporationInventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
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Patent number: 10152107Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.Type: GrantFiled: October 27, 2015Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
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Patent number: 9712144Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: September 3, 2015Date of Patent: July 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20170187363Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 9628059Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: June 18, 2015Date of Patent: April 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20170102732Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
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Publication number: 20170102761Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.Type: ApplicationFiled: October 27, 2015Publication date: April 13, 2017Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
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Patent number: 9608610Abstract: A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.Type: GrantFiled: September 11, 2015Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Mangal Prasad, Marshall D. Tiner, Xiaobin Yuan
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Patent number: 9543936Abstract: A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.Type: GrantFiled: June 22, 2015Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: Mangal Prasad, Marshall D. Tiner, Xiaobin Yuan
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Publication number: 20160373099Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: June 18, 2015Publication date: December 22, 2016Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20160373098Abstract: A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.Type: ApplicationFiled: June 22, 2015Publication date: December 22, 2016Inventors: MANGAL PRASAD, MARSHALL D. TINER, XIAOBIN YUAN
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Publication number: 20160373100Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: September 3, 2015Publication date: December 22, 2016Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20160373097Abstract: A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.Type: ApplicationFiled: September 11, 2015Publication date: December 22, 2016Inventors: MANGAL PRASAD, MARSHALL D. TINER, XIAOBIN YUAN
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Patent number: 9407247Abstract: A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller.Type: GrantFiled: October 22, 2014Date of Patent: August 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan J. Drake, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
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Patent number: 9298250Abstract: A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source.Type: GrantFiled: August 6, 2013Date of Patent: March 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Alan J. Drake, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
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Patent number: 9223295Abstract: A time-to-digital converter (TDC) in which a chain of inverters with finite propagation delays form a delay line in which a level transition applied to one end of the delay line from an input line produces a series of progressively delayed level transitions of alternating polarity along the delay line. Each inverter has an associated pass gate, with the output of the inverter together with the output of the preceding delay line element driving the complementary gate inputs of the pass gate. The complementary gate inputs of each pass gate are coupled to the corresponding delay line outputs in an alternating manner so that, as the level transitions traverse the delay line, the pass gates are progressively enabled to couple the input line to corresponding output lines to produce a series of progressively delayed level transitions of like polarity on those output lines.Type: GrantFiled: April 18, 2014Date of Patent: December 29, 2015Assignee: International Business Machines CorporationInventors: Marshall D Tiner, Xiaobin Yuan
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Publication number: 20150301505Abstract: A time-to-digital converter (TDC) in which a chain of inverters with finite propagation delays form a delay line in which a level transition applied to one end of the delay line from an input line produces a series of progressively delayed level transitions of alternating polarity along the delay line. Each inverter has an associated pass gate, with the output of the inverter together with the output of the preceding delay line element driving the complementary gate inputs of the pass gate. The complementary gate inputs of each pass gate are coupled to the corresponding delay line outputs in an alternating manner so that, as the level transitions traverse the delay line, the pass gates are progressively enabled to couple the input line to corresponding output lines to produce a series of progressively delayed level transitions of like polarity on those output lines.Type: ApplicationFiled: April 18, 2014Publication date: October 22, 2015Applicant: International Business Machines CorporationInventors: Marshall D. Tiner, Xiaobin Yuan