Patents by Inventor Marshall J. Fleming, Jr.

Marshall J. Fleming, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7521748
    Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Marshall J. Fleming, Jr., Mousa H. Ishaq, Steven M. Shank, Michael C. Triplett
  • Patent number: 7294554
    Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: November 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Marshall J. Fleming, Jr., Mousa H. Ishaq, Steven M. Shank, Michael C. Triplett
  • Patent number: 5294570
    Abstract: A substantial reduction in the foreign particulate matter contamination on surfaces, such as the surfaces of semiconductor wafers, is achieved by treating the surfaces with a solution comprising a strong acid and a very small amount of a fluorine-containing compound. A preferred method employs a solution containing sulfuric acid, hydrogen peroxide and a very small amount of hydrofluoric acid, which is effective in reducing foreign particulate matter contamination, without significant etching, of the surface being treated.
    Type: Grant
    Filed: January 29, 1992
    Date of Patent: March 15, 1994
    Assignee: International Business Machines Corporation
    Inventors: Marshall J. Fleming, Jr., William A. Syverson, Eric J. White