Abstract: A functional testing high-speed serial link system includes a testing controller that generates a functional testing program, and a device under test (DUT) that receives the functional testing program. The DUT includes a first logic circuit array that generates first results in response to executing the functional test program. The system also includes a supporting chip that receives the functional testing program. The supporting chip includes a second logic circuit array that generates second results in response to executing the functional test program. A physical data link establishes signal communication between the DUT and the supporting chip. The testing controller diagnoses the physical link based on a comparison between expected diagnostic results associated with the functional testing program, and at least one of the first results and the second results.

Abstract: A functional testing high-speed serial link system includes a testing controller that generates a functional testing program, and a device under test (DUT) that receives the functional testing program. The DUT includes a first logic circuit array that generates first results in response to executing the functional test program. The system also includes a supporting chip that receives the functional testing program. The supporting chip includes a second logic circuit array that generates second results in response to executing the functional test program. A physical data link establishes signal communication between the DUT and the supporting chip. The testing controller diagnoses the physical link based on a comparison between expected diagnostic results associated with the functional testing program, and at least one of the first results and the second results.

Abstract: Compact graphical representations of common test fail signatures and process related test fails are provided through methods of selecting, calculating and/or presenting information. The input may be a list of failing tests on a sample of devices under test from chip and/or wafer process fails. The failing tests are identified and then other tests that fail at the same time may be identified. Several graphical outputs are provided, including all possible combinations between test fails and between test fails and process fails. The dependencies are printed as sorted two dimensional bitmaps that are compact representations of the results using color codes. Subtraction of two independent bitmaps is provided, which eliminates common properties and emphasizes differences between multiple bitmaps which allows for quick identification of differences of process fails potentially different between the two different bitmaps indicating potential root causes for the selected one of the test fails.

Abstract: A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the netlist is performed, the N user logics in N macro test wrappers are instantiated resulting in N instantiated logics. After said instantiating the N user logics is performed, the N instantiated logics are processed. After said processing is performed, a result of said processing is back-annotated to the netlist.

Abstract: Compact graphical representations of common test fail signatures and process related test fails are provided through methods of selecting, calculating and/or presenting information. The input may be a list of failing tests on a sample of devices under test from chip and/or wafer process fails. The failing tests are identified and then other tests that fail at the same time may be identified. Several graphical outputs are provided, including all possible combinations between test fails and between test fails and process fails. The dependencies are printed as sorted two dimensional bitmaps that are compact representations of the results using color codes. Subtraction of two independent bitmaps is provided, which eliminates common properties and emphasizes differences between multiple bitmaps which allows for quick identification of differences of process fails potentially different between the two different bitmaps indicating potential root causes for the selected one of the test fails.

Abstract: A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the netlist is performed, the N user logics in N macro test wrappers are instantiated resulting in N instantiated logics. After said instantiating the N user logics is performed, the N instantiated logics are processed. After said processing is performed, a result of said processing is back-annotated to the netlist.