Abstract: An efficient polyphase half rate finite impulse response (FIR) filter module includes an odd/even sample delay line. The odd/even sample delay line includes two parallel paths of delays corresponding respectively to odd and even sample processing, i.e., every other sample. A first input sample is presented to the first register phase in the odd/even sample delay line and is fed directly to the third register phase bypassing the second register phase, the third register phase feeds directly into the fifth register phase, and so on until the ninth register phase of the odd/even sample delay line feeds directly into the eleventh register phase bypassing the tenth register phase. A second input sample skips over the first register phase and is presented directly to the second register phase in the odd/even sample delay line.