Patents by Inventor Martha Dudek

Martha Dudek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180236609
    Abstract: Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 23, 2018
    Inventors: Rajen S. SIDHU, Martha A. DUDEK, James C. MATAYABAS, JR., Michelle S. PHEN-GIVONI, Wei TAN
  • Patent number: 9950393
    Abstract: Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 24, 2018
    Assignee: INTEL CORPORATION
    Inventors: Rajen S. Sidhu, Martha A. Dudek, James C. Matayabas, Jr., Michelle S. Phen, Wei Tan
  • Patent number: 9283641
    Abstract: Embodiments of the present disclosure are directed towards flux materials for heated solder placement and associated techniques and configurations. In one embodiment, a method includes depositing a flux material on one or more pads of a package substrate, the flux material including a rosin material and a thixotropic agent and depositing one or more solder balls on the flux material disposed on the one or more pads, wherein depositing the one or more solder balls on the flux material is performed at a temperature greater than 80° C., and wherein the rosin material and the thixotropic agent are configured to resist softening at the temperature greater than 80° C. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: March 15, 2016
    Assignee: INTEL CORPORATION
    Inventors: Rajen S. Sidhu, Martha A. Dudek, Wei Tan
  • Patent number: 9257405
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Patent number: 9024453
    Abstract: Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package to be tailored, for example based on function. Functional package interconnects may vary one of more of at least material layer composition, layer thickness, number of layers, or a number of materials to achieve a particular function, for example based on an application of the component(s) interconnected or an application of the assembly as a whole. In embodiments, parameters of the multi-layered laminated structures are varied dependent on the interconnect location within an area of a substrate, for example with structures having higher ductility at interconnect locations subject to higher stress.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Ashay A. Dani, Martha A. Dudek
  • Patent number: 8920934
    Abstract: Hybrid solder for solder balls and filled paste are described. A solder ball may be formed of a droplet of higher temperature solder and a coating of lower temperature solder. This may be used with a solder paste that has an adhesive and a filler of low temperature solder particles, the filler comprising less than 80 weight percent of the paste. The solder balls and paste may be used in soldering packages for microelectronic devices. A package may be formed by applying a solder paste to a bond pad of a substrate, attaching a hybrid solder ball to each pad using the paste, and attaching the package substrate to a microelectronic substrate by reflowing the hybrid solder balls to form a hybrid solder interconnect.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Hongjin Jiang, Arun Kumar C. Nallani, Rajen S. Sidhu, Martha A. Dudek, Weihua Tang
  • Publication number: 20140319682
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Publication number: 20140291843
    Abstract: Hybrid solder for solder balls and filled paste are described. A solder ball may be formed of a droplet of higher temperature solder and a coating of lower temperature solder. This may be used with a solder paste that has an adhesive and a filler of low temperature solder particles, the filler comprising less than 80 weight percent of the paste. The solder balls and paste may be used in soldering packages for microelectronic devices. A package may be formed by applying a solder paste to a bond pad of a substrate, attaching a hybrid solder ball to each pad using the paste, and attaching the package substrate to a microelectronic substrate by reflowing the hybrid solder balls to form a hybrid solder interconnect.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Inventors: Hongjin Jiang, Arun Kumar C. Nallani, Rajen S. Sidhu, Martha A. Dudek, Weihua Tang
  • Patent number: 8809181
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Publication number: 20140225265
    Abstract: Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package to be tailored, for example based on function. Functional package interconnects may vary one of more of at least material layer composition, layer thickness, number of layers, or a number of materials to achieve a particular function, for example based on an application of the component(s) interconnected or an application of the assembly as a whole. In embodiments, parameters of the multi-layered laminated structures are varied dependent on the interconnect location within an area of a substrate, for example with structures having higher ductility at interconnect locations subject to higher stress.
    Type: Application
    Filed: March 29, 2012
    Publication date: August 14, 2014
    Inventors: Rajen S. Sidhu, Ashay A. Dadi, Martha A. Dudek
  • Publication number: 20140175160
    Abstract: A composition including a solder flux including a rosin material have a property to maintain a less than 10 percent drop in tackiness from an initial tackiness value of 20 gf to 120 gf over a temperature regime of 20° C. to 200° C. A composition including a solder powder; and a solder flux including a rosin material including a softening temperature of 150° C. to 200° C. and a molecular weight of 300 g/mol to 600 g/mol. A method including introducing a solder paste to one or more contact pads of a substrate, the solder paste including a solder powder and a solder flux including a rosin material including a softening temperature of 150° C. to 190° C. and a molecular weight of 300 g/mol to 600 g/mol; contacting the solder paste with a solder ball of a package substrate; and heating the solder paste.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Martha A. Dudek
  • Publication number: 20140124925
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Publication number: 20140084461
    Abstract: Embodiments of the present disclosure are directed towards flux materials for heated solder placement and associated techniques and configurations. In one embodiment, a method includes depositing a flux material on one or more pads of a package substrate, the flux material including a rosin material and a thixotropic agent and depositing one or more solder balls on the flux material disposed on the one or more pads, wherein depositing the one or more solder balls on the flux material is performed at a temperature greater than 80° C., and wherein the rosin material and the thixotropic agent are configured to resist softening at the temperature greater than 80° C. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Inventors: Rajen S. Sidhu, Martha A. Dudek, Wei Tan
  • Publication number: 20130341379
    Abstract: Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2011
    Publication date: December 26, 2013
    Inventors: Rajen S. Sidhu, Martha A. Dudek, James C. Matayabas, Michelle S. Phen, Wei Tan
  • Patent number: 8530058
    Abstract: A lead free solder consisting of a ternary eutectic composition of Sn-3.9Ag-0.7Cu with Ce in the amount of 0.5 to 2% by weight exhibits improved oxidation resistance increased ductility in comparison with other RE metals and is characterized by a homogeneous mixture of large grain CeSn3 intermetallics in a Sn beta phase. In solder applications, the joints with the solder are resistance to interfacial fracture by distributing the strain within the solder interface increasing impact resistance.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: September 10, 2013
    Assignee: Arizona Board of Regents, for and on behalf of Arizona State University
    Inventors: Nikhilesh Chawla, Martha Dudek