Abstract: A method of fabricating a vertical nano-transistor by forming holes in a thin metal film to provide the gate region for forming the channel region, applying insulation material to the walls of the holes and to the upper and lower surface of the metal film, applying semiconductor material in the insulated holes for forming the semiconductor channel region, and applying contacts for forming the source and drain regions.

Abstract: A method of fabricating a nano-scaled semiconductor by depositing upon a substrate, within the confines of a narrowly limited electric field, from an adjustable mixture of precursor gases containing different precursor compounds, nano-scaled deposits of common chemical compounds released in consequence of the precursor compounds breaking down upon the simultaneous or sequential application of a voltage exceeding a predetermined threshold value.

Abstract: A vertical nano-transistor having a source region, a drain region, a gate region and a semiconductor channel region between the source region and the drain region, the gate region being constituted by a metal film into which the transistor is embedded in such a manner that the gate region and the semiconductor channel region form a coaxial structure, the source region, the semiconductor channel region and the drain region being disposed vertically, and the gate region being electrically insulated from the source region, the drain region and the semiconductor channel region. The invention also relates to a method of producing the inventive transistor and a memory assembly.