Abstract: System and methods for shaped single carrier orthogonal frequency division multiplexing with low peak to average power ratio are provided. The system receives an input signal and modulates the input signal to form Dirichlet kernels in a time domain to generate an offset Dirichlet kernel output time array where each Dirichlet kernel has a main lobe and a plurality of side lobes. Modulating the input signal suppresses a peak to average power ratio of the offset Dirichlet kernel output time array by reducing the plurality of side lobes of each Dirichlet kernel and respective amplitudes of the side lobes.

Abstract: System and methods for shaped single carrier orthogonal frequency division multiplexing with low peak to average power ratio are provided. The system receives an input signal and modulates the input signal to form Dirichlet kernels in a time domain to generate an offset Dirichlet kernel output time array where each Dirichlet kernel has a main lobe and a plurality of side lobes. Modulating the input signal suppresses a peak to average power ratio of the offset Dirichlet kernel output time array by reducing the plurality of side lobes of each Dirichlet kernel and respective amplitudes of the side lobes.

Abstract: Systems and methods for shaped single carrier orthogonal frequency division multiplexing with low peak to average power ratio. The system receives an input signal and modulates the input signal to form Dirichlet kernels in a time domain to generate an offset Dirichlet kernel output time array where each Dirichlet kernel has a main lobe and a plurality of side lobes. The system modulates the input signal by receiving the input signal by an N-point time input array and transforming the N-point time input array to the frequency domain by a discrete Fourier transform to generate an N-point input frequency array. The system replicates the N-point input frequency array to generate an M-point input frequency array where M is greater than N and utilizes a filter to generate a shaped M-point output filtered frequency array by multiplying the M-point input frequency array and the filter.

Abstract: A method of setting a Radiofrequency, RF, signal level in a RF receiver comprising: estimating an error of the signal level due to signal level reaching a condition of jamming or clipping by correlating the signal level with a point of a characterization curve of jamming condition or with a point of a characterization curve of clipping condition (300), respectively; correcting the RF signal level based on the error; and, wherein: each of the characterization curves comprises a plurality of points comprising first points determined in a previously performed characterization at a point of measurement and groups of second points stepped between pairs of adjacent first points, said plurality of first points including at least three points defining at least two sections of the characterization curve.

Abstract: A method of operating a user equipment for measuring non-contiguous carriers comprises: changing a position of a local oscillator to be in the middle of the non-contiguous carriers; measuring the carriers simultaneously; estimating a power level of an interferer in a gap in the non-contiguous carriers which creates image interference; and compensating the measurement dependent on the interferer power level and an image rejection factor.

Abstract: A method of setting a Radiofrequency, RF, signal level in a RF receiver comprising:—estimating an error of the signal level due to signal level reaching a condition of jamming or clipping by correlating the signal level with a point of a characterisation curve of jamming condition or with a point of a characterisation curve of clipping condition (300), respectively;—correcting the RF signal level based on the error; and, wherein:—each of the characterisation curves comprises a plurality of points comprising first points determined in a previously performed characterisation at a point of measurement and groups of second points stepped between pairs of adjacent first points, said plurality of first points including at least three points defining at least two sections of the characterisation curve.

Abstract: A method of processing a paging message, the method being suitable for a User Equipment (UE) for a wireless telecommunication system, and comprising the steps of:—monitoring a Paging Indicator (PI) included in a Paging Indicator Channel (PICH) message;—upon reception (210) of a Paging Indicator (PI) relevant to said User Equipment, detecting and decoding a paging (PCH) channel in order to decode a corresponding paging message (220);—computing and checking the CRC (230) of said paging message and, in case of failure of the CRC check, performing the following steps:—performing (240, 250) a partial checking of said paging message, said partial checking being limited to a number of fields of said paging message;—determining whether said paging message is relevant to one single UE (260);—if said paging message is relevant to one single UE, replacing (261) the bits not relevant to said single UE by default bits and computing and checking (262) a new CRC—if the new CRC check succeeds, forwarding the processed paging

Abstract: A method of operating a user equipment for measuring non-contiguous carriers comprises: changing a position of a local oscillator to be in the middle of the non-contiguous carriers; measuring the carriers simultaneously; estimating a power level of an interferer in a gap in the non-contiguous carriers which creates image interference; and compensating the measurement dependent on the interferer power level and an image rejection factor.

Abstract: A method of processing a paging message, the method being suitable for a User Equipment (UE) for a wireless telecommunication system, and comprising the steps of:—monitoring a Paging Indicator (PI) included in a Paging Indicator Channel (PICH) message;—upon reception (210) of a Paging Indicator (PI) relevant to said User Equipment, detecting and decoding a paging (PCH) channel in order to decode a corresponding paging message (220);—computing and checking the CRC (230) of said paging message and, in case of failure of the CRC check, performing the following steps:—performing (240, 250) a partial checking of said paging message, said partial checking being limited to a number of fields of said paging message;—determining whether said paging message is relevant to one single UE (260);—if said paging message is relevant to one single UE, replacing (261) the bits not relevant to said single UE by default bits and computing and checking (262) a new CRC—if the new CRC check succeeds, forwarding the processed paging

Abstract: An integrated circuit configurable to encode data according to a number of coding schemes and to generate cyclic redundancy codes, includes a number of identical specific hardware cells, and each cell includes four outputs for binary signals, four inputs for binary signals, a buffer to delay by one clock period a binary value received on an input and to output a one-clock period delayed binary value, binary adders to perform XOR operations, configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, and controllable switch matrices external to each cell and able to electrically connect and disconnect inputs to or from outputs of another cell.

Abstract: A channel encoding method of calculating, using a programmable processor, a code identical with a code obtained with a hardware channel encoder. The method comprises:—a first step (112, 120; 222) of reading the result of a first sub-system of parallel XOR operations between shifted bits in a first pre-computed lookup table at a memory address determined from the value of the inputted bits, the first pre-computed lookup table storing any possible result of the first sub-system at respective memory addresses, and—at least a step (116, 124; 226) of carrying out an XOR operation between the read result and the result of a second sub-system of parallel XOR operations using an XOR instruction of the programmable processor.

Abstract: An integrated circuit configurable to encode data according to a number of coding schemes and to generate cyclic redundancy codes, includes a number of identical specific hardware cells, and each cell includes four outputs for binary signals, four inputs for binary signals, a buffer to delay by one clock period a binary value received on an input and to output a one-clock period delayed binary value, binary adders to perform XOR operations, configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, and controllable switch matrices external to each cell and able to electrically connect and disconnect inputs to or from outputs of another cell.

Abstract: The present invention relates to a method of performing time drift compensation in a receiver (200) and a receiver (200) for performing time drift compensation. The basic idea of the invention is that a signal is received at the receiver. A control pulse is produced after a certain number of chips of the received signal has been received. A variable delay that is applied to the received signal is controlled by means of the control pulse. The resulting delayed signal is supplied to demodulation units (202, 203) in the receiver, in which delayed signal chips have been omitted or duplicated. A compensation signal is supplied to the demodulation units in the receiver, and this compensation signal indicates whether chips have been omitted or duplicated in the delayed signal. Finally, the delayed signal is demodulated such that the demodulation units consider the omission or duplication of chips in the delayed signal.

Abstract: The present invention relates to a method of performing time drift compensation in a receiver (200) and a receiver (200) for performing time drift compensation. The basic idea of the invention is that a signal is received at the receiver. A control pulse is produced after a certain number of chips of the received signal has been received. A variable delay that is applied to the received signal is controlled by means of the control pulse. The resulting delayed signal is supplied to demodulation units (202, 203) in the receiver, in which delayed signal chips have been omitted or duplicated. A compensation signal is supplied to the demodulation units in the receiver, and this compensation signal indicates whether chips have been omitted or duplicated in the delayed signal. Finally, the delayed signal is demodulated such that the demodulation units consider the omission or duplication of chips in the delayed signal.