Abstract: Digital-to-analog converter having a reference voltage divider and a selection circuit by which the voltage at one of the nodal points of the reference voltage divider can be switched-through to the output of the converter. The selection circuit is controlled by selection signals coming from a decoder circuit by which the digital input signal is decoded. In addition, the converter includes a bias voltage divider which can apply different bias voltages to a level shifting circuit by which the signal level of the selection signals can be shifted.

Abstract: An interpolation circuit for an A/D converter comprises a first and a second pair of inputs (2, 2'; 3, 3') and at least three pairs of outputs (20, 20'; 24, 24'; 21, 21'). The pairs of inputs receive pairs of two input signals (V.sub.1, V.sub.1c, V.sub.5, V.sub.5c) which are substantially complementary to one another. At least two pairs of outputs (20, 20'; 24, 24') supply pairs of two substantially complementary output signals. A first output (21) of the third pair of outputs (21, 21') is coupled to a first input (2) of the first pair of inputs (2, 2'). The second output (21') of the third pair of outputs is connected to a circuit node other than one of the inputs of the first pair of inputs. This node may be, for example, the first input (3') of the second pair of inputs (FIG. 9). Another possibility is to make the node one end (38) of an impedance element (32) which has its other end coupled to the second input (2') of the first pair of inputs (FIG. 3).

Abstract: An integrated semiconductor circuit, in which the D.C. part of the wiring containing only D.C. information lies on a part of the insulating layer located on the surface which is considerably thinner than the parts of the insulating layer under wiring parts not forming part of the D.C. wiring. Preferably, for this purpose a substrate contact diffusion connected to a reference potential is provided under the D.C. wiring parts. As a result, H.F. interference signals on the D.C. wiring are reduced so that noise and distortion are considerably reduced.

Abstract: An interpolation circuit for use in an A/D converter comprises a first and a second pair of inputs (2, 2'; 3, 3') and at least three pairs of outputs (20, 20'; 24, 24'; 21, 21'). The pairs of inputs receive pairs of two input signals (V.sub.1, V.sub.1c, V.sub.5, V.sub.5c) which are substantially complementary to one another. At least two pairs of outputs (20, 20'; 24, 24') supply pairs of two substantially complementary output signals. A first output (21) of the third pair of outputs (21, 21') is coupled to a first input (2) of the first pair of inputs (2, 2'). The second output (21') of the third pair of outputs is connected to a circuit node which is not one of the inputs of the first pair of inputs. This node may be, for example, the first input (3') of the second pair of inputs (FIG. 9). Another possibility is to make the node one end (38) of an impedance element (32) whose other end is coupled to the second input (2') of the first pair of inputs (FIG. 3).

Abstract: An integrated resistor is constituted by a doped resistance body in a semiconductor substrate which is coated with a layer of insulating material having local apertures in which metal end contacts (2a, 3a) and tapping contacts (4a, 5a, 6a) are provided. The width of each tapping contact (4a, 5a, 6a) is smaller than the width of the doped zone and, viewed in the longitudinal direction of the resistance body, the tapping contacts (4a, 5a, 6a) do not overlap.

Abstract: In conventional digital-to-analog converters one of a number of multi-emitter transistors is driven by means of the select logics, the emitters of which are connected selectively to a group of data lines. The output circuits connected to the data lines further receive a reference voltage to be able to detect the condition on the data lines. In the analog converter according to the invention each data line is constructed so as to be complementary in which the emitters which in the prior art circuit arrangement are connected to the first group of data lines are coupled in the same manner to a first group of data lines while the remaining emitters are now connected to complementary lines from the second group. The output circuits which are connected to the data lines receive a logic signal of a data line and the complementary logic signal of the associated complementary data line. The result is that the voltage step which is presented to the inputs of the output circuits is twice as large.

Abstract: In an analog-to-digital converter circuit comprising a comparison circuit per tap of a potential divider. The comparison circuits are arranged in groups each controlling a respective differential amplifier. In a group only one output of each comparison circuit is connected to an output of the subsequent comparison circuit operating in the opposite sense and the odd outputs of the group of outputs thus obtained are connected via a first group of emitter followers to a first input of one of the differential amplifiers, while the even outputs are connected via a second group of emitter followers to a second input of this differential amplifier.