Abstract: A circuit and method for magnetic field detection is disclosed. A fluxgate sensor comprises a fluxgate having a first core and a second core. A sense coil has a first winding around the first fluxgate core and a second winding around the second fluxgate core. A fluxgate detection circuit is coupled to the sense coil and outputs a signal proportional to an external magnetic field applied to the fluxgate. A detection circuit is coupled to the first winding and outputs a signal that indicates whether voltage pulses have been detected on the first winding.

Abstract: A circuit and method for magnetic field detection is disclosed. A fluxgate sensor comprises a fluxgate having a first core and a second core. A sense coil has a first winding around the first fluxgate core and a second winding around the second fluxgate core. A fluxgate detection circuit is coupled to the sense coil and outputs a signal proportional to an external magnetic field applied to the fluxgate. A detection circuit is coupled to the first winding and outputs a signal that indicates whether voltage pulses have been detected on the first winding.

Abstract: This invention generally relates to the technical field of integrated circuits. More specifically the invention relates to output stages for providing an output signal, into which an integrated circuit may be used. An aspect relates to an integrated circuit capable of driving an external class-B output stage in a manner that allows providing a continuous output signal over the full range of desired outputs. The integrated circuit may comprise a class-AB output stage working in conjunction with the class-B output stage so as to provide a hybrid output stage. The integrated circuit may prevent dead band problems commonly faced when employing a class-B output stage. The integrated circuit may also reduce the quiescent current of the hybrid output stage. This may have further advantages, such as for example, the output stage producing less heat/power than needs to be dissipated.

Abstract: This invention generally relates to the technical field of integrated circuits. More specifically the invention relates to output stages for providing an output signal, into which an integrated circuit may be used. An aspect relates to an integrated circuit capable of driving an external class-B output stage in a manner that allows providing a continuous output signal over the full range of desired outputs. The integrated circuit may comprise a class-AB output stage working in conjunction with the class-B output stage so as to provide a hybrid output stage. The integrated circuit may prevent dead band problems commonly faced when employing a class-B output stage. The integrated circuit may also reduce the quiescent current of the hybrid output stage. This may have further advantages, such as for example, the output stage producing less heat/power than needs to be dissipated.

Abstract: An apparatus is provided that includes a drift trimming stage that includes a first current source providing a current with a first temperature dependency and a second current source providing a current with a second temperature dependency. The first and the second current source are coupled at a first node and configured to have equal currents at a first temperature. There is further a third current source providing a current with a third temperature dependency and a fourth current source providing a current with a fourth temperature dependency. The third current source and the fourth current source are coupled at a second node and configured to have equal currents at the first temperature. There is a first resistor coupled between the first node and a third node, a second resistor coupled between the second node and the third node. The first node and the second node are coupled to provide a combined voltage drop across the first resistor and the second resistor for reducing the offset drift.

Abstract: A single-slope ADC, particularly suitable for use in a massive-parallel ADC architecture in a readout circuit of a CMOS imager. A plurality of ramp signals are generated which define non-overlapping sub-ranges of the full input range. For each ADC channel, the sub-range in which the voltage of the input signal falls is determined, and the corresponding ramp signal is selected for use in the A/D conversion. Thus, the speed of the A/D conversion process can be increased and the power consumption decreased.

Abstract: An apparatus is provided that includes a drift trimming stage that includes a first current source providing a current with a first temperature dependency and a second current source providing a current with a second temperature dependency. The first and the second current source are coupled at a first node and configured to have equal currents at a first temperature. There is further a third current source providing a current with a third temperature dependency and a fourth current source providing a current with a fourth temperature dependency. The third current source and the fourth current source are coupled at a second node and configured to have equal currents at the first temperature. There is a first resistor coupled between the first node and a third node, a second resistor coupled between the second node and the third node. The first node and the second node are coupled to provide a combined voltage drop across the first resistor and the second resistor for reducing the offset drift.

Abstract: A single-slope ADC, particularly suitable for use in a massive-parallel ADC architecture in a readout circuit of a CMOS imager. A plurality of ramp signals are generated which define non-overlapping sub-ranges of the full input range. For each ADC channel, the sub-range in which the voltage of the input signal falls is determined, and the corresponding ramp signal is selected for use in the A/D conversion. Thus, the speed of the A/D conversion process can be increased and the power consumption decreased.