Patents by Inventor Martim Carbone

Martim Carbone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240028336
    Abstract: In one set of embodiments, an operating system (OS) kernel of a computer system can receive an invocation of a system call by a user program running on the computer system. The OS kernel can further fetch a plurality of subsequent instructions that will be executed by the user program after the invocation of the system call and decode the plurality of subsequent instructions into a plurality of decoded instructions. The OS kernel can then analyze whether the plurality of decoded instructions include an additional system call invocation and whether other decoded instructions that appear between the invocation of the system call and the additional system call invocation are viable for emulation by the OS kernel.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Inventors: Frederick Joseph Jacobs, Sam Scalise, Martim Carbone
  • Publication number: 20230082141
    Abstract: Techniques for supporting invocations of the RDTSC (Read Time-Stamp Counter) instruction, or equivalents thereof, by guest program code running within a virtual machine (VM), including guest program code running within a secure hardware enclave of the VM, are provided. In one set of embodiments, a hypervisor can activate time virtualization heuristics for the VM, where the time virtualization heuristics cause accelerated delivery of system clock timer interrupts to a guest operating system (OS) of the VM. The hypervisor can further determine a scaling factor to be applied to timestamps generated by one or more physical CPUs, where the timestamps are generated in response to invocations of a CPU instruction made by guest program code running within the VM, and where the scaling factor is based on the activated time virtualization heuristics. The hypervisor can then program the scaling factor into the one or more physical CPUs.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 16, 2023
    Inventors: VIVEK MOHAN THAMPI, ALOK NEMCHAND KATARIA, MARTIM CARBONE, DEEP SHAH
  • Patent number: 11507415
    Abstract: Techniques for supporting invocations of the RDTSC (Read Time-Stamp Counter) instruction, or equivalents thereof, by guest program code running within a virtual machine (VM), including guest program code running within a secure hardware enclave of the VM, are provided. In one set of embodiments, a hypervisor can activate time virtualization heuristics for the VM, where the time virtualization heuristics cause accelerated delivery of system clock timer interrupts to a guest operating system (OS) of the VM. The hypervisor can further determine a scaling factor to be applied to timestamps generated by one or more physical CPUs, where the timestamps are generated in response to invocations of a CPU instruction made by guest program code running within the VM, and where the scaling factor is based on the activated time virtualization heuristics. The hypervisor can then program the scaling factor into the one or more physical CPUs.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 22, 2022
    Assignee: VMWARE, INC.
    Inventors: Vivek Mohan Thampi, Alok Nemchand Kataria, Martim Carbone, Deep Shah
  • Patent number: 11327782
    Abstract: The present disclosure provides an approach for migrating the contents of an enclave, together with a virtual machine comprising the enclave, from a source host to a destination host. The approach provides a technique that allows the contents of the enclave to remain secure during the migration process, and also allows the destination host to decrypt the contents of the enclave upon receiving the contents and upon receiving the VM that includes the enclave. The approach allows for the VM to continue execution on the destination host. The enclave retains its state from source host to destination host. Applications using the enclave in the source host are able to continue using the enclave on the destination host using the data migrated from the source host to the destination host.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 10, 2022
    Assignee: VMware, Inc.
    Inventors: Alok Nemchand Kataria, Martim Carbone, Deep Shah
  • Patent number: 11170077
    Abstract: Techniques for verifying the integrity of application data using secure hardware enclaves are provided. In one set of embodiments, a client system can create a secure hardware enclave on the client system and load program code for an integrity verifier into the secure hardware enclave. The client system can further receive a dataset from a server system and store the dataset at a local storage or memory location, and receive, via the integrity verifier, a cryptographic hash of the dataset from the server system and store the received cryptographic hash at a memory location within the secure hardware enclave. Then, on a periodic basis, the integrity verifier can compute a cryptographic hash of the stored dataset, compare the computed cryptographic hash against the stored cryptographic hash, and if the computed cryptographic hash does not match the stored cryptographic hash, determine that the stored dataset has been modified.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: November 9, 2021
    Assignee: VMWARE, INC.
    Inventors: Alok Nemchand Kataria, Achindra Bhatnagar, Sachin Shinde, Martim Carbone, Deep Shah
  • Publication number: 20210216357
    Abstract: Techniques for supporting invocations of the RDTSC (Read Time-Stamp Counter) instruction, or equivalents thereof, by guest program code running within a virtual machine (VM), including guest program code running within a secure hardware enclave of the VM, are provided. In one set of embodiments, a hypervisor can activate time virtualization heuristics for the VM, where the time virtualization heuristics cause accelerated delivery of system clock timer interrupts to a guest operating system (OS) of the VM. The hypervisor can further determine a scaling factor to be applied to timestamps generated by one or more physical CPUs, where the timestamps are generated in response to invocations of a CPU instruction made by guest program code running within the VM, and where the scaling factor is based on the activated time virtualization heuristics. The hypervisor can then program the scaling factor into the one or more physical CPUs.
    Type: Application
    Filed: March 18, 2020
    Publication date: July 15, 2021
    Inventors: VIVEK MOHAN THAMPI, ALOK NEMCHAND KATARIA, MARTIM CARBONE, DEEP SHAH
  • Publication number: 20210124824
    Abstract: In a computer system operable at more than one privilege level, an interrupt security module handles interrupts without exposing a secret value of a register to virtual interrupt handling code that executes at a lower privilege level than the interrupt security module. The interrupt security module is configured to intercept interrupts generated while executing code at lower privilege levels. Upon receiving such an interrupt, the interrupt security module overwrites the secret value of the register with an unrelated constant. Subsequently, the interrupt security module generates a virtual interrupt corresponding to the interrupt and forwards the virtual interrupt to the virtual interrupt handling code. Advantageously, although the virtual interrupt handling code is able to determine the value of the register and consequently the unrelated constant, the virtual interrupt handling code is unable to determine the secret value.
    Type: Application
    Filed: January 5, 2021
    Publication date: April 29, 2021
    Inventors: Wei XU, Alok Nemchand KATARIA, Rakesh AGARWAL, Martim CARBONE
  • Patent number: 10922402
    Abstract: In a computer system operable at more than one privilege level, an interrupt security module handles interrupts without exposing a secret value of a register to virtual interrupt handling code that executes at a lower privilege level than the interrupt security module. The interrupt security module is configured to intercept interrupts generated while executing code at lower privilege levels. Upon receiving such an interrupt, the interrupt security module overwrites the secret value of the register with an unrelated constant. Subsequently, the interrupt security module generates a virtual interrupt corresponding to the interrupt and forwards the virtual interrupt to the virtual interrupt handling code. Advantageously, although the virtual interrupt handling code is able to determine the value of the register and consequently the unrelated constant, the virtual interrupt handling code is unable to determine the secret value.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: February 16, 2021
    Assignee: VMware, Inc.
    Inventors: Wei Xu, Alok Nemchand Kataria, Rakesh Agarwal, Martim Carbone
  • Publication number: 20210019166
    Abstract: The present disclosure provides an approach for migrating the contents of an enclave, together with a virtual machine comprising the enclave, from a source host to a destination host. The approach provides a technique that allows the contents of the enclave to remain secure during the migration process, and also allows the destination host to decrypt the contents of the enclave upon receiving the contents and upon receiving the VM that includes the enclave. The approach allows for the VM to continue execution on the destination host. The enclave retains its state from source host to destination host. Applications using the enclave in the source host are able to continue using the enclave on the destination host using the data migrated from the source host to the destination host.
    Type: Application
    Filed: September 5, 2019
    Publication date: January 21, 2021
    Inventors: ALOK NEMCHAND KATARIA, Martim Carbone, Deep Shah
  • Publication number: 20200218792
    Abstract: Techniques for verifying the integrity of application data using secure hardware enclaves are provided. In one set of embodiments, a client system can create a secure hardware enclave on the client system and load program code for an integrity verifier into the secure hardware enclave. The client system can further receive a dataset from a server system and store the dataset at a local storage or memory location, and receive, via the integrity verifier, a cryptographic hash of the dataset from the server system and store the received cryptographic hash at a memory location within the secure hardware enclave. Then, on a periodic basis, the integrity verifier can compute a cryptographic hash of the stored dataset, compare the computed cryptographic hash against the stored cryptographic hash, and if the computed cryptographic hash does not match the stored cryptographic hash, determine that the stored dataset has been modified.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 9, 2020
    Inventors: ALOK NEMCHAND KATARIA, Achindra Bhatnagar, Sachin Shinde, Martim Carbone, Deep Shah
  • Publication number: 20160147993
    Abstract: In a computer system operable at more than one privilege level, an interrupt security module handles interrupts without exposing a secret value of a register to virtual interrupt handling code that executes at a lower privilege level than the interrupt security module. The interrupt security module is configured to intercept interrupts generated while executing code at lower privilege levels. Upon receiving such an interrupt, the interrupt security module overwrites the secret value of the register with an unrelated constant. Subsequently, the interrupt security module generates a virtual interrupt corresponding to the interrupt and forwards the virtual interrupt to the virtual interrupt handling code. Advantageously, although the virtual interrupt handling code is able to determine the value of the register and consequently the unrelated constant, the virtual interrupt handling code is unable to determine the secret value.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 26, 2016
    Inventors: Wei XU, Alok Nemchand KATARIA, Rakesh AGARWAL, Martim CARBONE
  • Patent number: 9250942
    Abstract: At least one anomaly associated with at least one actual hardware element in a computer system having a plurality of hardware elements is addressed. The anomaly is detected, and, responsive to the detection, a virtualization layer is inserted between (i) an operating system of the computer system, and (ii) the plurality of hardware elements. Hardware emulation and/or selective hardware activation/deactivation are performed on the at least one actual hardware element by the virtualization layer. The insertion of the virtualization layer is accomplished in an on-the-fly manner.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Martim Carbone, Bernhard Jansen, HariGovind V. Ramasamy, Matthias Schunter, Axel Tanner, Diego M. Zamboni
  • Patent number: 9003402
    Abstract: A method and apparatus for injecting function calls into a virtual machine whereby a Function Call Injection (FCI) process is employed, through which a Secure Virtual Machine (SVM) is used to trigger desired function call invocations inside a Guest Virtual Machine (GVM) by externally manipulating the GVMs memory and CPU register contents using a security API. Once the triggered function is executed, control is then returned at the originating SVM invocation point. Therefore, the GVM state is manipulated to externally inject function calls, making it possible to create control appliances which do not require an in-GVM agent.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 7, 2015
    Assignee: Symantec Corporation
    Inventors: Martim Carbone, Matthew Conover, Bruce Robert Montague
  • Patent number: 8584254
    Abstract: Technologies pertaining to detecting accesses to monitored regions of memory and transmitting data to a protection system responsive to the detecting are described herein. A region of memory that includes objects in an object graph utilized by an operating system to determine which processes to execute and an order to execute such processes is monitored. If a process executing on a processor attempts to write to an object in the object graph, a field that is being written to is identified, and a determination is made regarding whether the field includes a pointer. Based upon whether the field includes a pointer, a type of write desirably undertaken by the object is ascertained, and an object event is transmitted to the protection system that informs the protection system of the type of write.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: November 12, 2013
    Assignee: Microsoft Corporation
    Inventors: Weidong Cui, Marcus Peinado, Martim Carbone
  • Publication number: 20130152207
    Abstract: Technologies pertaining to detecting accesses to monitored regions of memory and transmitting data to a protection system responsive to the detecting are described herein. A region of memory that includes objects in an object graph utilized by an operating system to determine which processes to execute and an order to execute such processes is monitored. If a process executing on a processor attempts to write to an object in the object graph, a field that is being written to is identified, and a determination is made regarding whether the field includes a pointer. Based upon whether the field includes a pointer, a type of write desirably undertaken by the object is ascertained, and an object event is transmitted to the protection system that informs the protection system of the type of write.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 13, 2013
    Applicant: Microsoft Corporation
    Inventors: Weidong Cui, Marcus Peinado, Martim Carbone
  • Publication number: 20090300307
    Abstract: A virtualization layer is inserted between (i) an operating system of a computer system, and (ii) at least one of a memory module and a storage module of the computer system. At least one of read access and write access to at least one portion of the at least one of a memory module and a storage module is controlled, with the virtualization layer. The insertion of the virtualization layer is accomplished in an on-the-fly manner (that is, without rebooting the computer system) An additional aspect includes controlling installation of a security program from the virtualization layer.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 3, 2009
    Applicant: International Business Machines Corporation
    Inventors: Martim Carbone, Bernhard Jansen, HariGovind V. Ramasamy, Matthias Schunter, Axel Tanner, Diego Zamboni
  • Publication number: 20090192780
    Abstract: At least one anomaly associated with at least one actual hardware element in a computer system having a plurality of hardware elements is addressed. The anomaly is detected, and, responsive to the detection, a virtualization layer is inserted between (i) an operating system of the computer system, and (ii) the plurality of hardware elements. Hardware emulation and/or selective hardware activation/deactivation are performed on the at least one actual hardware element by the virtualization layer. The insertion of the virtualization layer is accomplished in an on-the-fly manner.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: International Business Machines Corporation
    Inventors: Martim Carbone, Bernhard Jansen, HariGovind V. Ramasamy, Matthias Schunter, Axel Tanner, Diego M. Zamboni