Abstract: A data storage system stores a set of codewords in memory. The set of codewords are encoded in accordance with a joint nesting matrix specifying multiple layers of integrated interleaved codes, including first, second and third layers of integrated interleaved codes, and the set of codewords stored in the memory include first, second and third layers of parity information corresponding to the first, second and third layers of integrated interleaved codes. When decoding a first codeword and a first subgroup containing the first codeword fail, the system decodes a group of codewords that include two more subgroups of codewords, including the first subgroup of codewords, using the third layer parity information for the group of codewords. The second and third layers of integrated interleaved codes are configured to enable decoding of two codewords, in a subgroup of codewords, having errors beyond the correction capability of the first layer codes.

Abstract: A data storage system stores a set of codewords in memory. The set of codewords are encoded in accordance with a joint nesting matrix specifying multiple layers of integrated interleaved codes, including first, second and third layers of integrated interleaved codes, and the set of codewords stored in the memory include first, second and third layers of parity information corresponding to the first, second and third layers of integrated interleaved codes. When decoding a first codeword and a first subgroup containing the first codeword fail, the system decodes a group of codewords that include two more subgroups of codewords, including the first subgroup of codewords, using the third layer parity information for the group of codewords. The second and third layers of integrated interleaved codes are configured to enable decoding of two codewords, in a subgroup of codewords, having errors beyond the correction capability of the first layer codes.

Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.

Abstract: An apparatus and method for detecting analog signals representing patterns of n-bit RLL-encoded data read from a data storage device. R integrators each integrate the analog signal over successive time periods consisting of a preselected number n of bit cycles, where n>1, weighted by a preselected set of n orthogonal signals that are staircase functions which vary each bit cycle to provide R integrated weighted outputs. The R integrated weighted outputs are converted by a lookup table or read-only memory into an n-bit digital representation corresponding to a unique one of the n-bit analog data patterns.

Abstract: The error correction code capability of the linear recording density of a zone of contiguous recording tracks on a surface or volume having at lest two zones of different average linear recording density is adjusted. Each zone has associated therewith a parameter pair (r,R) defining the number of error correction bytes r to be appended to data blocks to form a codeword written to tracks within the zone and the number R.ltoreq.(r/2-1) of correctable errors in the event of a non-zero remainder detected upon readback of a codeword from a track within the zone. The r parameter controls the length of a shift register type encoder syndrome generator.

Abstract: A composite encoder/syndrome generating circuit computes both check symbols and error syndromes using a single set of multiplier devices with varying tap weights having values that provide a maximum preselected error correction capability but is readily adjustable, such as by programmable latches, to eliminate from the circuit selectable multiplier devices to reduce the error correction capability without requiring a change in the tap weight values. The circuit may be used to increase or decrease error correction capability (a) according to which of a plurality of concentric bands of recording tracks is being accessed in a banded direct access data storage device, (b) according to noise level as sensed in a data communications channel having an output subject to noise, or (c) according to changes in sending rates in a sending device that sends data at variable rates.

Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer compresses an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array.

Abstract: A bit-serial division method for computing the value v/u, where v and u are each n-bit vectors that are elements in a finite Galois field GF(2.sup.n) consisting of 2.sup.n elements. The n-bit components of each element in the field are coordinates of the element in a canonical basis of the field. Vector u is converted from canonical basis to a dual basis. Vector u in dual basis also comprises n bits in the finite field ordered according to an index i that takes on values from 0 to (n-1). All bits n of the converted vector u are loaded into a shift register in parallel, then converted from dual basis back to canonical basis to produce a single bit output w.sub.0 from a lookup table which generates bitwise the inverse of the n-bit vector u. The bits in the shift register are shifted (n-1) times to generate successive additional single bit outputs w.sub.i with said lookup table. Then each bit w.sub.i is multiplied by the vector v and a corresponding element c.sub.

Abstract: A method and means is described for correcting multiple error bursts in data recorded on a storage medium in blocks, comprising a plurality of subblocks. After reading the data, decoded block check syndromes are algebraically summed with estimated block check syndromes to provide a set of syndromes for a code for locating subblocks having an error burst. This set of syndromes is decoded to identify each subblock having an error burst. Concurrently block level syndromes are computer to identify the locations and values of errors within the subblocks having error bursts. During writing, the data in all subblocks of a block is encoded and block level syndromes are generated for these subblocks. These block level syndromes are multiplied by a series of preselected weighting factors (.alpha..sup.1 . . ..alpha..sup.1(B-1)) according to the location index 1 of the sublock within the block and as multiplied, each is stored in a different one of B buffers.

Abstract: This disclosure concerns for generating asymmetrically constrained run-length-limited encoded data from a serialized binary string of 1's and 0's. The method comprises the steps of encoding the input data bits using a run-length-limited constraint in the form of M/N (d,k), where M is the number of input data bits, N is the number of output bits associated therewith, d is the minimum number of 0 data bits between adjacent data bit 1's, and k is the maximum number of 0 data bits between adjacent 1's; and alternating the values of d and k between a set (d.sub.1, k.sub.1) and a set (d.sub.2, k.sub.2), respectively, where d.sub.1 .noteq.d.sub.2. The apparatus comprises means for generating N output data bits in response to M input data bits and for generating data bit 0's between data bit 1's based upon a run-length-limited coding constraints (d.sub.1, k.sub.1) and (d.sub.2, k.sub.2), where constraints (d.sub.1, k.sub.1) and (d.sub.2, k.sub.2) apply alternately to runs of zeroes between output data ones.

Abstract: Uncompressed data is represented in a constrained code for transmission through a channel which may include record media. A d,k code having a code rate of m/n is employed. "d" represents the minimum number of successive zeros in the channel code while k represents the maximum number of zeros in the channel code. "n" is an integer representing the number of code bits in a channel group. The encoding and decoding follows a sliding block coding and decoding algorithm. In the channel coding, the number of successive ones is limited to being not less than two, in some coding it can be a value of d-1. The modification of the d,k code results in decreasing error propagation while increasing the recorded information density. This increase is achieved by increasing the channel code dictionary.