Abstract: A brewing assembly with a bean hopper assembly that comprises a housing and a tub at least partially located in the housing. The tub defines a pocket configured to hold beans, and an opening extends through the tub to route beans into a provided grinder. A knob extends through the opening and includes a first locking member that includes a locked position where the tub is fixed to the housing, and an unlocked position where the tub is selectively fixed to the housing. A push button assembly includes a second locking member that is selectively moveable to an actuated position when the first locking member is in the unlocked position to release the tub, and where the tub is fixed to the housing when the second locking member is in the actuated position and the first locking member is in the locked position.

Abstract: The present invention relates to the field of medicine, specifically the field of bacterial infection and treatment thereof.

Abstract: There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y?1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0?x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an AI processing system comprising said FPGA device (100).

Abstract: The present disclosure provides a compound comprising a modified tetracycline derivative, covalently coupled through a linker to a low-hydrophobicity bioactive molecule useful for treating neurodegenerative diseases, wherein the modified tetracycline derivative is optionally defined by the following formula:

Abstract: A production cell includes: at least one robot arranged to handle products; at least one buffer area for intermediate storage of products inside the production cell; a vision system with cameras arranged to determine, based on images from the cameras, the identity and the location of objects in the production cell a plurality of production modules, each production module comprising at least one Hardware Module configured to process products; and a plurality of module attachment locations, each module attachment location being configured to connect with an interface section of a production module through at least a physical connection and a power connection.

Abstract: The present disclosure relates to a method for a weighting graph comprising nodes representing entities and edges representing relationships between entities in accordance with one or more domains. The method comprises: pre-processing the graph comprising assigning weights to the nodes and/or the edges of the graph in accordance with a specific domain of the domains, wherein the weight indicates a domain specific data quality problem of attribute values representing an edge of the edges and/or an entity involved in that edge. The weighted graph may be provided for enabling a processing of the graph in accordance with the specific domain.

Abstract: A method of generating customizable goal representation is disclosed. A request from a user to view a goal representation is received. A flexible goal ontology is accessed that comprises one or more goal entities, one or more goal relationships between the goal entities, or one or more goal properties, the one or more goal properties including one or more metadata attributes relating to the one or more goal entities. A set of mapping rules is obtained that defines mappings between one or more goals. The set of mapping rules is evaluated to assemble a customized goal representation tailored to the user. The customized goal representation is updated based on a revaluation of the mapping rules affected by changes to the one or more goal entities, the one or more goal relationships, or the one or more properties.

Abstract: Image reconstruction systems and methods include providing sensitivity maps for coils of a magnetic resonance imaging (MRI) system to a neural network. The systems and methods also include providing interleaved k-space data to the neural network, wherein the interleaved k-space data includes partial k-space data interleaved with zeros, or synthesized k-space data, to provide an extended field of view (FOV) different from a FOV utilized during acquisition of the partial k-space data, wherein the partial k-space data were obtained during a scan of a region of interest with the MRI system. The systems and methods further include outputting, from the neural network, a final reconstructed MR image based at least on the sensitivity maps and the interleaved k-space data, wherein the final reconstructed MR image includes the FOV utilized during the acquisition of the partial k-space data.

Abstract: There is provided a vertical high-electron-mobility transistor, HEMT (100), comprising: a drain contact (410), a nanowire layer (500) arranged on the drain contact (410) and comprising at least one vertical nanowire (510) and a supporting material (520) laterally enclosing the at least one vertical nanowire (510), a heterostructure (600) arranged on the nanowire layer and comprising an AIGaN-layer (610) and a GaN-layer (620) together forming a heterojunction, at least one source contact (420a, 420b) in contact with the heterostructure (600), and a gate contact (430) in contact with the heterostructure (600), arranged above the at least one vertical nanowire (510), wherein the at least one vertical nanowire (510) is forming an electron transport channel between the drain contact and the heterostructure. There is also provided a method for producing a vertical HEMT (100).

Abstract: Apparatuses and methods relating to semiconductor layer structures are disclosed. A method for producing a semiconductor layer structure ay involve providing a Si substrate comprising a top surface, forming a first semiconductor layer on the substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures, arranged perpendicularly to the top surface of the substrate, the first semiconductor layer comprising AIN, and epitaxially growing a second semiconductor layer which laterally and vertically encloses the plurality of vertical nanowire structures thereby encapsulating dislocations in shells around the nanowires, wherein the second semiconductor layer comprises AlxGa1-xN, wherein 0:x:0.95.

Abstract: A method performed by a node in a telecommunications network for managing faults includes obtaining predictions of faults in the telecommunications network and time intervals in which the faults are predicted to occur. The method then includes determining possible actions that could be performed to address the predicted faults and associated resource usages to perform the possible actions, and selecting actions to perform, from the possible actions, in order to address the predicted faults, based on the predicted time intervals and the determined resource usages.

Abstract: There is provided a monolithic microwave integrated circuit, MMIC, front-end module which may include: a gallium nitride structure supported by a silicon substrate, a silicon-based transmit/receive switch having a transmit mode and a receive mode, a transmit amplifier configured to amplify an outgoing signal to be transmitted by said MMIC front-end module, wherein said transmit amplifier is electrically connected to said transmit/receive switch, wherein said transmit amplifier comprises a gallium nitride high-electron-mobility transistor, HEMT, formed in said gallium nitride structure. The MMIC front-end module may further include a receive amplifier configured to amplify an incoming signal received by said MMIC front-end module, wherein said receive amplifier is electrically connected to said transmit/receive switch, wherein said receive amplifier may include a gallium nitride HEMT formed in said gallium nitride structure.

Abstract: There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising AlxGa1-xN, wherein 0?x?0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0?y?0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.

Abstract: There is provided a monolithic microwave integrated circuit, MMIC, front-end module (100) comprising: a gallium nitride structure (110) supported by a silicon substrate (120); a silicon-based transmit/receive switch (130) having a transmit mode and a receive mode; a transmit amplifier (112) configured to amplify an outgoing signal to be transmitted by said MMIC front-end module, wherein said transmit amplifier is electrically connected (132) to said transmit/receive switch, wherein said transmit amplifier comprises a gallium nitride high-electron-mobility transistor, HEMT, (114) formed in said gallium nitride structure; and a receive amplifier (113) configured to amplify an incoming signal received by said MMIC front-end module, wherein said receive amplifier is electrically connected (133) to said transmit/receive switch, wherein said receive amplifier comprises a gallium nitride HEMT (115) formed in said gallium nitride structure.

Abstract: There is provided an induction machine (100) comprising a rotor (120); a stator (140); and a phase-shift oscillator (160). The stator comprises: a first winding (141); and a second winding (142), arranged at a first angle (101) relative to said first winding. The phase-shift oscillator comprises: a transistor (170), the transistor (170) being a high-electron mobility transistor, HEMT; and a phase-shift network (180). The first winding is connected to a first node (181) of the phase-shift network and wherein the second winding is connected to a second node (182) of the phase-shift network, wherein the phase-shift oscillator is configured to provide a first phase electric signal at the first node and a second phase electric signal at the second node, wherein a difference between the first and second phase corresponds to the first angle. There is also provided an electric aircraft propulsion system comprising the induction machine.

Abstract: A device for performing electrolysis of water is disclosed. The device may include a semiconductor structure with a surface and an electron guiding layer below said surface, the electron guiding layer of the semiconductor structure being configured to guide electron movement in a plane parallel to the surface. The electron guiding layer of the semiconductor structure may include an InGaN quantum well or a heterojunction, the heterojunction being a junction between AlN material and GaN material or between AlGaN material and GaN material and at least one metal cathode arranged on the surface of the semiconductor structure. The device may further include at least one photoanode arranged on the surface of the semiconductor structure, wherein the at least one photoanode may include a plurality of quantum dots of InxGa(1-x)N material, wherein 0.4?x?1. A system including such a device is also disclosed.

Abstract: There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120)comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y?1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0?x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an Al processing system comprising said FPGA device (100).

Abstract: A reinforced thin-film device is disclosed. The reinforced thin-film device comprising: a substrate having a top surface for supporting an epilayer; a mask layer patterned with a plurality of nanosize cavities disposed on said substrate to form a needle pad; a thin-film of, relative to the substrate, lattice-mismatched semiconductor disposed on said mask layer, wherein said thin-film comprises a plurality of in parallel spaced semiconductor needles of said lattice-mismatched semiconductor embedded in said thin-film, wherein said plurality of semiconductor needles are vertically disposed in the axial direction towards said substrate in said plurality of nanosize cavities of said mask layer; a, relative to the substrate, lattice-mismatched semiconductor epilayer provided on said thin-film and supported thereby; and a FinFET transistor arranged on the lattice-mismatched semiconductor epilayer.

Abstract: There is provided an AC-DC converter circuit (100) for high power charging of an electrical battery. The circuit comprises an input rectifier comprising a first node and a second node. The input rectifier (110) is configured to receive an AC voltage at the first node (112) and provide a rectified voltage at the second node (114). The circuit further comprises a first transistor (120), comprising a first gate node (122), a first source node (124), and a first drain node (126). The first drain node is connected to the second node of the input rectifier. The first gate node is connected to a ground node (170). The circuit further comprises a second transistor (130), comprising a second gate node (132), a second source node (134), and a second drain node (136). The second drain node is connected to the first source node. The second transistor materially corresponds to the first transistor.

Abstract: A device for performing electrolysis of water is disclosed. The device comprising: a semiconductor structure comprising a surface and an electron guiding layer below said surface, the electron guiding layer of the semiconductor structure being configured to guide electron movement in a plane parallel to the surface, the electron guiding layer of the semiconductor structure comprising an InGaN quantum well or a heterojunction, the heterojunction being a junction between AlN material and GaN material or between AlGaN material and GaN material; at least one metal cathode arranged on the surface of the semiconductor structure; and at least one photoanode arranged on the surface of the semiconductor structure, wherein the at least one photoanode comprises a plurality of quantum dots of InxGa(1?x)N material, wherein 0.4?x?1. A system comprising such device is also disclosed.