Abstract: A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

Abstract: A power integrated circuit comprising at least one III-nitride high voltage high-electron-mobility transistor (power HEMT), the power HEMT comprising a heterojunction formed between a GaN layer and an AlGaN layer, and a slew rate protection circuit. The slew rate protection circuit comprising a clamping transistor electrically connected between a gate terminal and a source terminal of the power HEMT, and a detection circuit electrically connected between a drain terminal and the source terminal of the power HEMT, wherein an output of the detection circuit is electrically connected to a gate terminal of the clamping transistor. The detection circuit is configured to output a signal to turn-on the clamping transistor when a transient voltage greater than a threshold transient voltage is observed across the drain and the source terminals of the power HEMT.

Abstract: A semiconductor switch comprising a first main terminal, a second main terminal, and a control terminal, the semiconductor switch further comprising: a III-nitride high-electron-mobility transistor (HEMT), the III-nitride HEMT comprising a first source terminal, a first drain terminal, and a first gate terminal; a first interface circuit operatively connected to the control terminal and to the first gate terminal; and a short-circuit detection circuit operatively connected to the first drain terminal and the first source terminal, the short-circuit detection circuit being configured to: sense a short-circuit across the first drain terminal and the first source terminal; and transmit a short-circuit detection signal to the first interface circuit, the first interface circuit being configured, upon receipt of the short-circuit detection signal, to cause the III-nitride HEMT to turn off, and/or to cause a voltage across the first gate terminal to be reduced.

Abstract: A processor-implemented method for learning an antenna offset for perception-aided wireless communication includes receiving a stream of inputs from one or more sensors. A dynamic segmentation mask corresponding to an object observed by the one or more sensors is generated based on the stream of inputs. A trajectory for the one or more sensors is determined based on the dynamic segmentation mask. An antenna position for the object is predicted based on the trajectory.

Abstract: A processor-implemented method for beam management using region information and region-specific codebook generation includes receiving a stream of inputs from one or more sensors. A region of a user equipment (UE) is determined using a digital twin that models an environment observed by the network device based on the stream of inputs. The region is determined based on a position of the UE in the environment. A beam estimate is generated based on a codebook selected based on the region.

Abstract: A processor-implemented method for multimodal beam management implemented by a network device includes receiving, by the network device, a stream of inputs from one or more sensors. The network device generates a digital twin modeling an environment of a region observed by the one or more sensors. The digital twin includes one or more objects detected based on the stream of inputs. The network device manages a wireless communication signal beam for communicating with at least one user equipment (UE) in the region observed by the one or more sensors based at least in part on the digital twin.

Abstract: An Ill-nitride semiconductor based heterojunction power device is disclosed and includes a first and second heterojunction transistors formed on a substrate. The first and second heterojunction transistors include first and second Ill-nitride semiconductor regions formed over the substrate. The first Ill-nitride semiconductor region includes a first heterojunction, a first terminal connected to the first Ill-nitride semiconductor region, a second terminal laterally spaced from the first terminal and connected to the first Ill-nitride semiconductor region, and a first gate region over the first Ill-nitride semiconductor region between the first and second terminals.

Abstract: A transmitter housing of an automation field device is a single-chamber housing with an aperture. The field device comprises a printed circuit board arranged in the transmitter housing, the printed circuit board comprising: a first rigid and flat section and a second rigid and flat section; at least one flexible and bent section; wherein both rigid sections are connected to each other only via the at least one flexible, bent section, wherein the first rigid section is accessible from the aperture and forms a connecting region comprising at least one connecting element for connecting at least one cable, and wherein the first rigid section and the second rigid section are arranged relative to each other at a first angle of between 60° and 120°, in particular between 80° and 100°.

Abstract: A III-nitride semiconductor based heterojunction integrated circuit (IC), comprising a substrate; a III-nitride semiconductor region located over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of a second conductivity type; a power device comprising: a first terminal operatively connected to the III-nitride semiconductor region; a second terminal operatively connected to the III-nitride semiconductor region and laterally spaced from the first terminal; a gate structure located above the III-nitride semiconductor region and laterally spaced between the first and second terminals; and a control gate terminal operatively connected to the gate structure, wherein the control gate terminal is configured such that a potential applied to the control gate terminal modulates and controls a current flow through the two-dimensional carrier gas between the first and second terminals.

Abstract: We disclose a Ill-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor (19) formed on a substrate, the first heterojunction transistor comprising: a first Ill-nitride semiconductor region formed over the substrate, wherein the first Ill-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal (8) operatively connected to the first Ill-nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first Ill-nitride semiconductor region; a first gate terminal (10) formed over the first Ill-nitride semiconductor region between the first terminal and the second terminal.

Abstract: An III-nitride power semiconductor based heterojunction device comprising a first heterojunction and a second heterojunction transistor, wherein the second heterojunction transistor has a substantially identical structure to the first heterojunction transistor, and wherein the second heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a scale factor X, where X is larger than 1.

Abstract: A III-nitride power semiconductor based heterojunction device comprising a substrate, a first terminal, a second terminal, a control terminal configured to receive an input switching signal during an active mode of operation and to not receive the input switching signal during a stand-by mode of operation, and an active heterojunction transistor formed on the substrate.

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for beam selection using machine learning. A plurality of data samples corresponding to a plurality of data modalities is accessed. A plurality of features is generated by, for each respective data sample of the plurality of data samples, performing feature extraction based at least in part on a respective modality of the respective data sample. The plurality of features is fused using one or more attention-based models, and a wireless communication configuration is generated based on processing the fused plurality of features using a machine learning model.

Abstract: A method for producing a probe of a thermal flowmeter for measuring mass flow of a medium in a measuring tube, wherein a probe core is provided arranged loosely in a probe sleeve having a longitudinal axis, wherein the probe sleeve is deformed relative to the longitudinal axis completely radially in the direction of the probe core by means of high energy rate forming, wherein a material-locking connection between probe sleeve and probe core results and a rod is formed, wherein the rod represents a base body that is used for probe production, wherein a deformation speed reaches values greater than 100 m/s, and wherein the high energy rate forming includes explosive forming or magnetic forming.

Abstract: Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.

Abstract: An integrated circuit is provided which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

Abstract: The present disclosure relates to an edge detection circuit configured to receive an input signal comprising one or more falling or falling edges and provide an output signal comprising pulses or spikes corresponding to the one or more rising or falling edges. The edge detection circuit comprises a passive differentiator circuit configured to receive an input and provide a differentiator output signal that that is proportional to the rate of change of the input, and a comparator circuit operably connected to a voltage source. The comparator circuit is configured to receive the differentiator output signal, compare the differentiator output signal to a threshold voltage; and output a pulse or spike signal based on the comparison to the threshold voltage.

Abstract: We describe a smart high voltage/power III-nitride semiconductor based diode or rectifier comprising first and second terminals, and further comprising an active device (e.g. a transistor such as a GaN HEMT transistor), a sensing device (e.g. a sensing diode/transistor), a sensing load (e.g. a resistor), wherein the smart high voltage/power III-nitride semiconductor based diode or rectifier is configured to output a sensing signal corresponding a current through the sensing device and/or a voltage drop across the sensing load, wherein the sensing signal is indicative of a current flowing between the first and second terminal when a bias is applied between the first and second terminals.

Abstract: We describe an integrated circuit is disclosed which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

Abstract: A III-nitride semiconductor based heterojunction power device including: a first heterojunction transistor formed on a substrate, and a second heterojunction transistor formed on the substrate. One of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor. The enhancement mode transistor acts as a main power switch, and the depletion mode transistor acts as a start-up component.