Patents by Inventor Martin Bartels
Martin Bartels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240081594Abstract: A method for operating a self-propelled cleaning device is proposed, wherein the cleaning device comprises a preferably hinged cover and a distance meter for measuring the distance of the cleaning device from objects in its environment. According to the invention, the distance meter is used to detect an open position of the cover.Type: ApplicationFiled: September 6, 2023Publication date: March 14, 2024Inventors: Roman ORTMANN, Jascha BARTELS, Martin ENGELHARDT, Matthias HÜSIG
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Publication number: 20230119033Abstract: A method includes providing a substrate having a main surface, forming a layer of thermally insulating material on the main surface, forming strips of phase change material on the layer of thermally insulating material such that strips of phase change material are separated from the main surface by thermally insulating material, forming first and second RF terminals on the main surface that are laterally spaced apart from one another and connected to the strips of phase change material, and forming a heater structure having heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material, wherein each of the strips of phase change material includes multiple outer faces, and wherein portions of both outer faces from the strips of phase change material are disposed against one of the heating elements.Type: ApplicationFiled: December 21, 2022Publication date: April 20, 2023Inventors: Dominik Heiss, Martin Bartels, Christoph Glacer, Christoph Kadow, Matthias Markert, Hans Taddiken, Hans-Dieter Wohlmuth
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Patent number: 11563174Abstract: A switching device includes first and second RF terminals disposed over a substrate, one or more strips of phase change material connected between the first and second RF terminals, a region of thermally insulating material that separates the one or more strips of phase change material from the substrate, and a heater structure comprising one or more heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material. Each of the one or more strips of phase change material includes a first outer face and a second outer face opposite from the first outer face. For each of the one or more strips of phase change material, at least portions of both of the first and second outer faces are disposed against one of the heating elements.Type: GrantFiled: April 9, 2020Date of Patent: January 24, 2023Assignee: Infineon Technologies AGInventors: Dominik Heiss, Martin Bartels, Christoph Glacer, Christoph Kadow, Matthias Markert, Hans Taddiken, Hans-Dieter Wohlmuth
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Publication number: 20210320250Abstract: A switching device includes first and second RF terminals disposed over a substrate, one or more strips of phase change material connected between the first and second RF terminals, a region of thermally insulating material that separates the one or more strips of phase change material from the substrate, and a heater structure comprising one or more heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material. Each of the one or more strips of phase change material includes a first outer face and a second outer face opposite from the first outer face. For each of the one or more strips of phase change material, at least portions of both of the first and second outer faces are disposed against one of the heating elements.Type: ApplicationFiled: April 9, 2020Publication date: October 14, 2021Inventors: Dominik Heiss, Martin Bartels, Christoph Glacer, Christoph Kadow, Matthias Markert, Hans Taddiken, Hans-Dieter Wohlmuth
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Patent number: 10804354Abstract: A radio frequency resistor element comprises a resistive polysilicon trace, an isolation component and a semiconductor substrate. The resistive polysilicon trace is located above the isolation component. The isolation component is laterally at least partially surrounded by a modified semiconductor region located above the semiconductor substrate and having a higher charge carrier recombination rate than the semiconductor substrate.Type: GrantFiled: March 23, 2018Date of Patent: October 13, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Hans Taddiken, Martin Bartels, Andrea Cattaneo, Henning Feick, Christian Kuehn, Anton Steltenpohl
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Patent number: 10490642Abstract: A semiconductor device includes a semiconductor substrate having a first side, and a trench structure having a bottom and a sidewall. The bottom has at least first and second bottom portions laterally adjacent to one another. Each bottom portion has a concave shape with a ridge formed between the first and second bottom portions. An insulating material covers the sidewall and first bottom portion of the trench structure while leaving the second bottom portion uncovered. A mesa region extends to the first side of the substrate and forms the sidewall of the trench structure. The device also includes a first silicide layer on a top region of the mesa region, a second silicide layer on the second bottom portion of the trench structure, a first metal layer on and in contact with the first silicide layer, and a second metal layer on and in contact with the second silicide layer.Type: GrantFiled: March 19, 2018Date of Patent: November 26, 2019Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Rolf Weis, Martin Bartels, Marko Lemke, Stefan Tegen
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Patent number: 10276494Abstract: Memory cells and corresponding memory arrays are provided. The memory cell comprises a fusable element and a bipolar transistor arranged adjacent to the fusable element.Type: GrantFiled: July 19, 2017Date of Patent: April 30, 2019Assignee: Infineon Technologies AGInventors: Kerstin Kaemmer, Martin Bartels, Henning Feick
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Publication number: 20180286941Abstract: A radio frequency resistor element comprises a resistive polysilicon trace, an isolation component and a semiconductor substrate. The resistive polysilicon trace is located above the isolation component. The isolation component is laterally at least partially surrounded by a modified semiconductor region located above the semiconductor substrate and having a higher charge carrier recombination rate than the semiconductor substrate.Type: ApplicationFiled: March 23, 2018Publication date: October 4, 2018Inventors: Hans Taddiken, Martin Bartels, Andrea Cattaneo, Henning Feick, Christian Kuehn, Anton Steltenpohl
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Publication number: 20180212031Abstract: A semiconductor device includes a semiconductor substrate having a first side, and a trench structure having a bottom and a sidewall. The bottom has at least first and second bottom portions laterally adjacent to one another. Each bottom portion has a concave shape with a ridge formed between the first and second bottom portions. An insulating material covers the sidewall and first bottom portion of the trench structure while leaving the second bottom portion uncovered. A mesa region extends to the first side of the substrate and forms the sidewall of the trench structure. The device also includes a first silicide layer on a top region of the mesa region, a second silicide layer on the second bottom portion of the trench structure, a first metal layer on and in contact with the first silicide layer, and a second metal layer on and in contact with the second silicide layer.Type: ApplicationFiled: March 19, 2018Publication date: July 26, 2018Inventors: Rolf Weis, Martin Bartels, Marko Lemke, Stefan Tegen
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Patent number: 9984917Abstract: A method for manufacturing a semiconductor device in accordance with various embodiments may include: forming an opening in a first region of a semiconductor substrate, the opening having at least one sidewall and a bottom; implanting dopant atoms into the at least one sidewall and the bottom of the opening; configuring at least a portion of a second region of the semiconductor substrate laterally adjacent to the first region as at least one of an amorphous or polycrystalline region; and forming an interconnect over at least one of the first and second regions of the semiconductor substrate.Type: GrantFiled: May 21, 2014Date of Patent: May 29, 2018Assignee: Infineon Technologies AGInventors: Christian Kuehn, Martin Bartels, Henning Feick, Dirk Offenberg, Anton Steltenpohl, Hans Taddiken, Ines Uhlig
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Patent number: 9941375Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.Type: GrantFiled: January 27, 2017Date of Patent: April 10, 2018Assignee: Infineon Technologies Dresden GmbHInventors: Rolf Weis, Martin Bartels, Marko Lemke, Stefan Tegen
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Publication number: 20180061756Abstract: One time programmable memory cell and memory array Memory cells and corresponding memory arrays are provided. The memory cell comprises a fusable element and a bipolar transistor arranged adjacent to the fusable element.Type: ApplicationFiled: July 19, 2017Publication date: March 1, 2018Inventors: Kerstin Kaemmer, Martin Bartels, Henning Feick
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Patent number: 9882600Abstract: According to various embodiments, a switching device may include: an antenna terminal; a switch including a first switch terminal and a second switch terminal, the first switch terminal coupled to the antenna terminal, the switch including at least one transistor at least one of over or in a silicon region including an oxygen impurity concentration of smaller than about 3×1017 atoms per cm3; and a transceiver terminal coupled to the second switch terminal, wherein the transceiver terminal is at least one of configured to provide a signal received via the antenna terminal or configured to receive a signal to be transmitted via the antenna terminal.Type: GrantFiled: February 5, 2014Date of Patent: January 30, 2018Assignee: INFINEON TECHNOLOGIES AGInventors: Christian Kuehn, Martin Bartels, Henning Feick, Dirk Offenberg, Anton Steltenpohl, Hans Taddiken, Ines Uhlig
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Publication number: 20170222010Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.Type: ApplicationFiled: January 27, 2017Publication date: August 3, 2017Inventors: Rolf Weis, Martin Bartels, Marko Lemke, Stefan Tegen
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Publication number: 20170062276Abstract: A layer stack is formed on a main surface of a semiconductor layer, wherein the layer stack includes a dielectric capping layer and a metal layer between the capping layer and the semiconductor layer. Second portions of the layer stack are removed to form gaps between remnant first portions. Adjustment structures of a second dielectric material are formed in the gaps. An interlayer of the first or a third dielectric material is formed that covers the adjustment structures and the first portions. Contact trenches are formed that extend through the interlayer and the capping layer to metal structures formed from remnant portions of the metal layer in the first portions, wherein the capping layer is etched selectively against the auxiliary structures.Type: ApplicationFiled: August 26, 2016Publication date: March 2, 2017Inventors: Stefan Tegen, Martin Bartels, Thomas Bertrams, Marko Lemke, Rolf Weis
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Publication number: 20170040317Abstract: A semiconductor device includes a semiconductor substrate having a first side. At least a first doping region is formed in the semiconductor substrate. The first doping region has a laterally varying doping dosage and/or a laterally varying implantation depth.Type: ApplicationFiled: August 2, 2016Publication date: February 9, 2017Inventors: Stefan Tegen, Martin Bartels, Marko Lemke, Ralf Rudolf, Rolf Weis
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Publication number: 20170012110Abstract: A method includes forming a first trench in a semiconductor body between two semiconductor fins, filling the first trench with a first filling material, partially removing the first filling material by forming a second trench such that the second trench has a lower aspect ratio than the first trench, and at least partially filling the second trench with a second filling material so as to form a continuous material layer on the first filling material. A semiconductor device includes a first trench in a semiconductor body between two semiconductor fins, the first trench being filled with a first filling material, and a second trench having a lower aspect ratio than the first trench and being at least partially filled with a second filling material which forms a continuous material layer on the first filling material.Type: ApplicationFiled: July 8, 2016Publication date: January 12, 2017Inventors: Rolf Weis, Martin Bartels, Marko Lemke, Stefan Tegen
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Publication number: 20160343848Abstract: A Transistor arrangement in a semiconductor body comprises a power transistor with at least two transistor cells, each transistor cell arranged in a semiconductor fin of the semiconductor body and with a voltage limiting device with at least two device cells. Each device cell is arranged adjacent a transistor cell in the semiconductor fin of the respective transistor cell and the voltage limiting device is separated from the power transistor by a dielectric layer.Type: ApplicationFiled: May 18, 2016Publication date: November 24, 2016Inventors: Martin Bartels, Marko Lemke, Ralf Rudolf, Stefan Tegen, Rolf Weis
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Publication number: 20160149032Abstract: A semiconductor device includes at least two transistor cells. Each of these at least two transistor cells includes: a drain region, a drift region, and a body region in a semiconductor fin of a semiconductor body; a source region adjoining the body region; a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric; and a field electrode dielectrically insulated from the drift region by a field electrode dielectric, and connected to the source region. The field electrode dielectric is arranged in a first trench between the semiconductor fin and the field electrode. The at least two transistor cells include a first transistor cell, and a second transistor cell. The semiconductor fin of the first transistor cell is separated from the semiconductor fin of the second transistor cell by a second trench different from the first trench.Type: ApplicationFiled: November 17, 2015Publication date: May 26, 2016Inventors: Martin Bartels, Rolf Weis
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Publication number: 20150340277Abstract: A method for manufacturing a semiconductor device in accordance with various embodiments may include: forming an opening in a first region of a semiconductor substrate, the opening having at least one sidewall and a bottom; implanting dopant atoms into the at least one sidewall and the bottom of the opening; configuring at least a portion of a second region of the semiconductor substrate laterally adjacent to the first region as at least one of an amorphous or polycrystalline region; and forming an interconnect over at least one of the first and second regions of the semiconductor substrate.Type: ApplicationFiled: May 21, 2014Publication date: November 26, 2015Applicant: Infineon Technologies AGInventors: Christian Kuehn, Martin Bartels, Henning Feick, Dirk Offenberg, Anton Steltenpohl, Hans Taddiken, Ines Uhlig