Abstract: An oscillator and a method for producing an improved oscillator that will generate an accurate frequency when encountering a vibration. The oscillator and method uses a crystal with minimal cross-axis coupling. Further, a first accelerometer produced using MEMS technology is used. The first accelerometer is positioned inside of the oscillator so that the accelerometer accurately measures any vibration encountered by the oscillator. The first accelerometer and the crystal are maintained at constant temperature to minimize phase shifts and gain variations.

Abstract: An oscillator and a method for producing an improved oscillator that will generate an accurate frequency when encountering a vibration. The oscillator and method uses a crystal with minimal cross-axis coupling. Further, a first accelerometer produced using MEMS technology is used. The first accelerometer is positioned inside of the oscillator so that the accelerometer accurately measures any vibration encountered by the oscillator. The first accelerometer and the crystal are maintained at constant temperature to minimize phase shifts and gain variations.

Abstract: A charge pump configuration for matching a charge pump to prevailing conditions is described. The charge pump configuration according to the invention has a charge pump having a plurality of interconnected pump stages, with at least one respective pump capacitor, and a closed-loop control device. The closed-loop control device is configured such that it bridges or turns off at least one of the pump stages on the basis of the conditions that are to be taken into account. The pump stages needed by the charge pump configuration are optimally chosen for the present operating point on a basis of input and output voltages and currents, which allows the efficiency of the charge pump configuration to be set in optimum fashion.

Abstract: The charge pump generates high voltages for integrated semiconductor circuits. The charge pump has a plurality of pump stages with at least one power transistor each for generating a pump voltage on a power path. The power transistor has a freely switchable bulk terminal with which a well structure of the power transistor can be maintained at a predetermined potential via a well charge path that is substantially separate from the power path.

Abstract: A temperature-compensated semiconductor resistor includes two series-connected semiconductor resistance elements having mutually inverse resistive temperature-dependent responses in a temperature range of interest. The semiconductor resistance elements are preferably made of doped polycrystalline semiconductor material such as polycrystalline silicon that is oppositely doped, i.e. n-doped and p-doped, respectively. A semiconductor integrated circuit, in particular a CMOS circuit, containing a semiconductor resistor, is also provided.

Abstract: A circuit configuration for measuring or calibrating current of components in memory elements, preferably, EPROM or EEPROM memory elements, includes a memory cell field, a reference cell field, a current comparator, a digital-analog converter receiving a digital signal having digital values and outputting predetermined current values based upon receiving corresponding ones of the digital values, a first switch having an output connected to a first input of the current comparator, a first input connected to the memory cell field, and a second input connected to the reference cell field, and a second switch having an output connected to a second input of the current comparator, a first input connected to the reference cell field, and a second input connected to the digital-analog converter. The second switch can have a third input to be connected to an external current source.

Abstract: The object is to discharge a first capacitor from a high voltage to a low voltage. To this end, the one electrode of the first capacitor is linked with the one electrode of a second capacitor via a FET path. The other two electrodes of the two capacitors are connected to reference potential. A voltage source with its internal resistance is connected in parallel to the second capacitor. A discharge path leads from the one electrode of the first capacitor from the paths of two FET and a protective resistor to the reference potential. A current path leads from the one electrode of the second capacitor to the reference potential via the paths of two additional FET. A control unit switches on the discharge path. Once the voltage of the first capacity has decreased to the required lower value, the discharge path is blocked while a holding path is opened.

Abstract: The object is to discharge a first capacitor from a high voltage to a low voltage. To this end, the one electrode of the first capacitor is linked with the one electrode of a second capacitor via a FET path. The other two electrodes of the two capacitors are connected to reference potential. A voltage source with its internal resistance is connected in parallel to the second capacitor. A discharge path leads from the one electrode of the first capacitor from the paths of two FET and a protective resistor to the reference potential. A current path leads from the one electrode of the second capacitor to the reference potential via the paths of two additional FET. A control unit switches on the discharge path. Once the voltage of the first capacity has decreased to the required lower value, the discharge path is blocked while a holding path is opened.

Abstract: The charge pump generates high voltages for integrated semiconductor circuits. The charge pump has a plurality of pump stages with at least one power transistor each for generating a pump voltage on a power path. The power transistor has a freely switchable bulk terminal with which a well structure of the power transistor can be maintained at a predetermined potential via a well charge path that is substantially separate from the power path.

Abstract: A circuit configuration for measuring or calibrating current of components in memory elements, preferably, EPROM or EEPROM memory elements, includes a memory cell field, a reference cell field, a current comparator, a digital-analog converter receiving a digital signal having digital values and outputting predetermined current values based upon receiving corresponding ones of the digital values, a first switch having an output connected to a first input of the current comparator, a first input connected to the memory cell field, and a second input connected to the reference cell field, and a second switch having an output connected to a second input of the current comparator, a first input connected to the reference cell field, and a second input connected to the digital-analog converter. The second switch can have a third input to be connected to an external current source.

Abstract: A temperature-compensated semiconductor resistor includes two series-connected semiconductor resistance elements having mutually inverse resistive temperature-dependent responses in a temperature range of interest. The semiconductor resistance elements are preferably made of doped polycrystalline semiconductor material such as polycrystalline silicon that is oppositely doped, i.e. n-doped and p-doped, respectively. A semiconductor integrated circuit, in particular a CMOS circuit, containing a semiconductor resistor, is also provided.

Abstract: A charge pump configuration for matching a charge pump to prevailing conditions is described. The charge pump configuration according to the invention has a charge pump having a plurality of interconnected pump stages, with at least one respective pump capacitor, and a closed-loop control device. The closed-loop control device is configured such that it bridges or turns off at least one of the pump stages on the basis of the conditions that are to be taken into account. The pump stages needed by the charge pump configuration are optimally chosen for the present operating point on a basis of input and output voltages and currents, which allows the efficiency of the charge pump configuration to be set in optimum fashion.

Abstract: An EEPROM with two-transistor memory cells with source-side selection, and a method for triggering such a EEPROM are described. The EEPROM and the method are distinguished in that the programming voltage required to program a memory cell is delivered via a source line. As a result the EEPROM can be protected in a simple way against unintended loss of the data stored in it.

Abstract: An apparatus for voltage multiplication of the kind required, for example, for programming flash EEPROMs. The apparatus has the advantage that comparatively simple and good regulation of the output voltage can be produced even in integrated circuits in which severe fluctuations in the supply voltage may be allowed.

Abstract: A circuit configuration for producing negative voltages includes a first transistor having a first connection connected to an input connection, a second connection connected to an output connection of the circuit configuration and a gate connection connected through a first capacitor to a first clock signal connection. A second transistor has a first connection connected to the gate connection of the first transistor, a second connection connected to the second connection of the first transistor and a gate connection connected to the first connection of the first transistor. A second capacitor has a first connection connected to the second connection of the first transistor and a second connection connected to a second clock signal connection. The transistors are MOS transistors produced in a triple well.