Abstract: An autonomous ground treatment appliance, in particular a robotic lawnmower, includes a housing, a running gear, a control unit, at least one wheel unit, and a sensor unit. The control unit is configured to control the autonomous ground treatment appliance. The at least one wheel unit is mounted on the housing so as to be at least partially movable relative to the housing. The sensor unit is configured to ascertain a position of the wheel unit relative to the housing.

Abstract: An autonomous ground treatment appliance, in particular a robotic lawnmower, includes a housing, a running gear, a control unit, at least one wheel unit, and a sensor unit. The control unit is configured to control the autonomous ground treatment appliance. The at least one wheel unit is mounted on the housing so as to be at least partially movable relative to the housing. The sensor unit is configured to ascertain a position of the wheel unit relative to the housing.

Abstract: A system for processing packet streams includes a first packet queuing circuitry connected between a first processor and a second processor and operable to queue packets for transfer from the first processor to the second processor. The system includes a second packet queuing circuitry connected between the first processor and the second processor and operable to queue packets for transfer from the second processor to the first processor. The first processor is programmed to transfer secure packets to the second processor via the first queuing circuitry for security processing and the second processor is programmed to return the security-processed packets to the first processor via the second queuing circuitry.

Abstract: A video decoding circuit comprising: a first video data processor; a second video data processor; and a connection connecting the first video data processor and the second data processor; wherein the first video data processor is arranged to receive a first signal comprising encoded video data, process the first signal to provide a second signal and output the second signal. The first video data processor being arranged to process the first signal dependent on at least part of the received first signal. The second video data processor is arranged to receive at least a part of the second signal, process the at least a part of the second signal to provide a third signal, and output the third signal, the second and third signals comprising a decoded video image stream. The second video data processor is arranged to process the at least part of the second signal dependent on at least part of the at least part of second signal.

Abstract: A multimode filter that is versatile for digital signal processing including in-loop processing (de-blocking and de-ringing), post processing (de-blocking and de-ringing), and overlap smoothing. A flexi-standard filter includes the multimode filter. An electronic device includes the flexi-standard filter. A process for digital signal processing includes in-loop processing (de-blocking and de-ringing), post processing (de-blocking and de-ringing), and overlap smoothing.

Abstract: Systems and methods are disclosed that includes a data-bus, system memory, a first processor arranged to receive an input stream, and a second processor programmed to apply one or more security algorithms to secure packets of the input stream to generate at least partially security-processed packets.

Abstract: Systems and methods are disclosed that include a data-bus, system memory, a first processor arranged to receive an input stream, and a second processor programmed to apply one or more security algorithms to secure packets of the input stream to generate at least partially security-processed packets.

Abstract: An optical device includes at least one optical fiber cable receiving area for receiving at least one optical fiber cable, the receiving area being sized to receive a covering for covering at least a portion of the transition area, and at least one optical fiber cable transition portion disposed at the receiving area, the optical fiber cable transition portion being responsive to and supporting the covering when pressure from the covering is applied to the transition area and the covering and said transition area together form a buffer zone associated with at least a portion of the cable receiving area. Methods include providing a multi-port optical connection terminal having a stub cable port; connecting a stub cable assembly including a stub cable to the stub cable port; and forming a sloped buffer zone between the stub cable port and the stub cable to relieve stress in the stub cable.

Abstract: An optical device includes at least one optical fiber cable receiving area for receiving at least one optical fiber cable, the receiving area being sized to receive a covering for covering at least a portion of the transition area, and at least one optical fiber cable transition portion disposed at the receiving area, the optical fiber cable transition portion being responsive to and supporting the covering when pressure from the covering is applied to the transition area and the covering and said transition area together form a buffer zone associated with at least a portion of the cable receiving area. Methods include providing a multi-port optical connection terminal having a stub cable port; connecting a stub cable assembly including a stub cable to the stub cable port; and forming a sloped buffer zone between the stub cable port and the stub cable to relieve stress in the stub cable.

Abstract: Data is discrete cosine transformed and streamed to a processor where quantized and inverse quantized blocks are generated. A second streaming data connection streams the inverse quantized blocks to an inverse discrete cosine transform block to generate reconstructed prediction error macroblocks. An addition circuit adds each reconstructed prediction error macroblock and its corresponding predictor macroblock to generate a respective reconstructed macroblock. The quantized macroblocks are zig-zag scanned, run level coded and variable length coded to generate and encoded bitstream.

Abstract: Data is discrete cosine transformed and streamed to a processor where quantized and inverse quantized blocks are generated. A second streaming data connection streams the inverse quantized blocks to an inverse discrete cosine transform block to generate reconstructed prediction error macroblocks. An addition circuit adds each reconstructed prediction error macroblock and its corresponding predictor macroblock to generate a respective reconstructed macroblock. The quantized macroblocks are zig-zag scanned, run level coded and variable length coded to generate and encoded bitstream.

Abstract: A multimode filter that is versatile for digital signal processing including in-loop processing (de-blocking and de-ringing), post processing (de-blocking and de-ringing), and overlap smoothing. The present disclosure further discloses a flexi-standard filter comprising the multimode filter. The present disclosure also discloses an electronic device comprising the flexi-standard filter. The present disclosure finally discloses a process for digital signal processing that includes in-loop processing (de-blocking and de-ringing), post processing (de-blocking and de-ringing), and overlap smoothing.

Abstract: A video decoding circuit comprising: a first video data processor; a second video data processor; and a connection connecting the first video data processor and the second data processor; wherein the first video data processor is arranged to receive a first signal comprising encoded video data, process the first signal to provide a second signal and output the second signal. The first video data processor being arranged to process the first signal dependent on at least part of the received first signal. The second video data processor is arranged to receive at least a part of the second signal, process the at least a part of the second signal to provide a third signal, and output the third signal, the second and third signals comprising a decoded video image stream. The second video data processor is arranged to process the at least part of the second signal dependent on at least part of the at least part of second signal.

Abstract: Data is discrete cosine transformed and streamed to a processor where quantized and inverse quantized blocks are generated. A second streaming data connection streams the inverse quantized blocks to an inverse discrete cosine transform block to generate reconstructed prediction error macroblocks. An addition circuit adds each reconstructed prediction error macroblock and its corresponding predictor macroblock to generate a respective reconstructed macroblock. The quantized macroblocks are zig-zag scanned, run level coded and variable length coded to generate and encoded bitstream.

Abstract: A picture compression circuit includes a video memory and an encoding unit connected to the video memory in order to read a picture by macroblocks to subject these macroblocks to a discrete cosine transform, a quantification and a variable length coding, and to read in the memory predictor macroblocks of another picture and to subtract these predictor macroblocks from the currently processed macroblocks. A motion estimation unit can be connected to the video bus and to the encoding unit, to receive through the video bus a macroblock currently processed and a search window, in order to search in the window for a predictor macroblock. The difference of position between the predictor macroblock and the currently processed macroblock is provided as a motion estimation vector to the encoding unit.

Abstract: A quantizer that divides each digital word of a series of sequences by a quantification coefficient which may vary from one sequence to the other. The quantizer includes a delay circuit that receives the words to be divided and delays the words by one sequence; a divider that receives the output of the delay circuit; another circuit that provides, for each sequence, the maximum value of the ratio between each word and a limit value that can be provided by the quantizer; a comparator that receives the maximum value of the ratio and the quantification coefficient; a switch, cooperating with the comparator, that provides to the divider a division coefficient equal either to the quantification coefficient if the quantification coefficient is higher than the maximum value of the ratio, or alternatively the maximum value of the ratio.

Abstract: A circuit determines a quantification coefficient to be provided to a quantizer incorporated in a picture macroblock compression chain. A first counter counts the number of bits of each macroblock compressed by the compression chain. A first accumulator integrates the difference between each number provided by the first counter and a target, and provides a value corresponding to the quantification coefficient. A microprocessor provides the first accumulator with an initial value and a target at each N macroblocks. Parameters that characterize the current compression process are determined so that the microprocessor determines the target and the initial value to be provided to the first accumulator.