Abstract: A device (2) for determining optimal equalizer settings (setE_opt) for an equalizer (1) for equalizing a pulse amplitude modulation signal (L0, L1, L2, L3) comprises an estimator section (21) configured for receiving at least a part of the equalized pulse amplitude modulation signal (L0?, L1?, L2?, L3?) from the equalizer (1), and for receiving an offset signal (offS), and for generating an estimator signal (estS) indicative of a percentage of signal levels of the at least a part of the equalized pulse amplitude modulation signal (L0?, L1?, L2?, L3?) which are larger or smaller than the offset signal (offS).

Abstract: A device (2) for determining optimal equalizer settings (setE_opt) for an equalizer (1) for equalizing a pulse amplitude modulation signal (L0, L1, L2, L3) comprises an estimator section (21) configured for receiving at least a part of the equalized pulse amplitude modulation signal (L0?, L1?, L2?, L3?) from the equalizer (1), and for receiving an offset signal (offS), and for generating an estimator signal (estS) indicative of a percentage of signal levels of the at least a part of the equalized pulse amplitude modulation signal (L0?, L1?, L2?, L3?) which are larger or smaller than the offset signal (offS).

Abstract: Disclosed is a decoder circuit for a pulse amplitude modulation signal and a method of decoding a pulse amplitude modulation signal. The pulse amplitude modulation signal has a zeroth signal level, a first signal level, a second signal level and a third signal level. The decoder circuit comprises a first decision circuit, and a mapping circuit. The first decision circuit receives the pulse amplitude modulation signal and generates a low output signal for the first and the zeroth signal level, and generates a high output signal for the third and the second signal level. The mapping circuit receives the pulse amplitude modulation signal and generates a low output signal for the second and first signal level, and generates a high output signal for the third and zeroth signal level. Optionally, the decoder circuit comprises a logic circuit.

Abstract: Disclosed is a decoder circuit for a pulse amplitude modulation signal and a method of decoding a pulse amplitude modulation signal. The pulse amplitude modulation signal has a zeroth signal level, a first signal level, a second signal level and a third signal level. The decoder circuit comprises a first decision circuit, and a mapping circuit. The first decision circuit receives the pulse amplitude modulation signal and generates a low output signal for the first and the zeroth signal level, and generates a high output signal for the third and the second signal level. The mapping circuit receives the pulse amplitude modulation signal and generates a low output signal for the second and first signal level, and generates a high output signal for the third and zeroth signal level. Optionally, the decoder circuit comprises a logic circuit.

Abstract: Multiple pins extend from the outside to the inside of an optical sub-assembly. A light receiver or a light transmitter is arranged inside the optical sub-assembly. A receiver circuit and transmitter circuit (TX) are arranged inside the optical sub-assembly and connected between the multiple pins and the light receiver and the light transmitter. The receiver circuit comprises a receiver communication interface in order to transform an output signal of the light receiver into a communication signal, and wherein the transmitter circuit comprises a transmitter communication interface to transform a communication signal into an input signal of the light transmitter. A control interface is connected with the receiver circuit and the transmitter circuit arranged inside the optical sub-assembly, wherein the control interface is connectable to two of the multiple pins.

Abstract: Multiple pins extend from the outside to the inside of an optical sub-assembly. A light receiver or a light transmitter is arranged inside the optical sub-assembly. A receiver circuit and transmitter circuit (TX) are arranged inside the optical sub-assembly and connected between the multiple pins and the light receiver and the light transmitter. The receiver circuit comprises a receiver communication interface in order to transform an output signal of the light receiver into a communication signal, and wherein the transmitter circuit comprises a transmitter communication interface to transform a communication signal into an input signal of the light transmitter. A control interface is connected with the receiver circuit and the transmitter circuit arranged inside the optical sub-assembly, wherein the control interface is connectable to two of the multiple pins.

Abstract: The invention relates to a symmetrical optical receiver comprising a photodiode (Ph) and a symmetrical transimpedance amplifier (TIA). The cathode (K) or respectively the anode (A) of the photodiode (Ph) is connected via a first capacitor (C1) or respectively second capacitor (C2), to the first input or respectively second input, of the symmetrical transimpedance amplifier (TIA). By means of first means (1) or respectively second means (2), a current corresponding to the low-pass-filtered cathode voltage or respectively anode voltage, is conducted into the cathode (K) or respectively conducted away from the anode (A). With the symmetrical optical receiver according to the invention, a low level lower cut-off frequency is able to be achieved with comparatively small coupling capacitors (C1, C2) and with a small circuitry outlay. Moreover, a relatively high voltage drop across the photodiode can be created even with small supply voltages.