Patents by Inventor Martin Brox

Martin Brox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240321340
    Abstract: Methods, systems, and devices for techniques and devices to reduce bus cross talk are described. Adjacent conductive lines in a bus of a memory system may be electrically coupled if both conductive lines are concurrently driven to a high-state. For example, the bus may include a logic circuit coupled between the adjacent conductive lines, which may selectively couple the conductive lines based on the voltage applied to each conductive line. In some examples, the logic circuit may include an input coupled to the control signals of the drivers associated with the adjacent conductive lines. If both control signals are concurrently high, the logic circuit may activate a transistor to couple the conductive lines. Such electrical coupling may reduce or eliminate the capacitive coupling between the two conductive lines when both are driven to a high state, which may result in increased reliability of signals in the conductive lines.
    Type: Application
    Filed: February 27, 2024
    Publication date: September 26, 2024
    Inventors: Martin Brox, Milena Tsvetkova Ivanov, Natalija Jovanovic
  • Patent number: 12099406
    Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output is transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.
    Type: Grant
    Filed: June 23, 2023
    Date of Patent: September 24, 2024
    Inventors: Stefan Dietrich, Martin Brox, Michael Dieter Richter, Thomas Hein, Ronny Schneider, Natalija Jovanovic
  • Patent number: 12086005
    Abstract: Methods, systems, and devices for tracking a reference voltage (also referred to as VREFD) after boot-up are described. For example, a host device or a memory device may determine a temperature value associated with the memory device. The host device or the memory device may select a reference voltage offset value for the memory device based on mapping the temperature value associated with the memory device to a relationship between reference voltage offset values and temperature differential values associated with the memory device. The host device or the memory device may adjust a reference voltage value associated with the memory device based on the reference voltage offset value. The host device, or the memory device, may operate the memory device in accordance with the reference voltage value based on adjusting the reference voltage value.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: September 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Martin Brox, Thomas Hein, Wolfgang Anton Spirkl, Andrea Sorrentino, Peter Mayer
  • Patent number: 12081331
    Abstract: Methods, systems, and devices for operating memory cell(s) using adapting the current on a channel are described. A current on a channel may be adapted during a transition period between signaling a first logic value over the channel and signaling a second (e.g. subsequent) logic value over the channel. Adapting the current may include increasing or decreasing the current on the channel during the transition period. The degree of adaptation may be based on a difference between the first logic value and the subsequent logic value. In some cases, a logic circuit may be configured to determine a difference between the first and subsequent logic value. The logic circuit may be further configured to communicate the difference to an adaptive driver. And the adaptive driver may adapt a current of the channel based on the communicated difference.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 3, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Martin Brox, Peter Mayer, Michael Dieter Richter, Thomas Hein, Wolfgang Anton Spirkl
  • Publication number: 20240290373
    Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.
    Type: Application
    Filed: March 7, 2024
    Publication date: August 29, 2024
    Inventors: Martin Brox, C. Omar Benitez, Johnathan L. Gossi, Christopher John Kawamura
  • Publication number: 20240240995
    Abstract: Methods, systems, and devices for temperature sensor linearization techniques are described. A temperature sensor associated with a semiconductor device may include a first circuit and a second circuit. The second circuit may be configured to determine that a first temperature, associated with the semiconductor device and indicated by one or more first bits generated by the first circuit, is within a first temperature range of a total temperature range measurable by the temperature sensor. The second circuit may be configured to generate and output, based on the first temperature being within the first temperature range, one or more second bits indicating a second temperature associated with the semiconductor device. The second circuit may generate the one or more second bits by applying, to the one or more first bits, a first-order operation corresponding to the first temperature range and associated with correcting an error of the first temperature.
    Type: Application
    Filed: January 4, 2024
    Publication date: July 18, 2024
    Inventors: Luiza Souza Correa, Julius Löckemann, Elena Cabrera Bernal, Martin Brox, Jun Tan
  • Patent number: 12027231
    Abstract: Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: July 2, 2024
    Inventors: Martin Brox, Wolfgang Anton Spirkl, Thomas Hein, Michael Dieter Richter, Peter Mayer
  • Patent number: 12019900
    Abstract: Methods, systems, and devices for temperature-based memory management are described. A system may include a memory device and a host device. The host device may identify a temperature (e.g., of the memory device). The host device may determine a value for a parameter for operating the memory device—such as a timing, voltage, or frequency parameter—based on the temperature of the memory device. The host device may transmit signaling to the memory device or another component of the system based on the value of the parameter. In some cases, the host device may determine the temperature of the memory device based on an indication (e.g., provided by the memory device). In some cases, the host device may determine the temperature of the memory device based on a temperature of the host device or a temperature of another component of the system.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: June 25, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Peter Mayer, Thomas Hein, Wolfgang Anton Spirkl, Martin Brox, Michael Dieter Richter
  • Patent number: 12015476
    Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Stefan Dietrich, Thomas Hein, Natalija Jovanovic, Ronny Schneider, Michael Dieter Richter, Martin Brox
  • Publication number: 20240185909
    Abstract: Methods, systems, and devices for command clock structure are described. A memory device may receive a command to determine a relationship (e.g., a phase relationship) between an external clock and an internally generated clock. In some examples, the memory device may execute the command and may report (e.g., to a host device) whether the command is successfully or unsuccessfully executed. The memory device may report the successful or unsuccessful execution of the command by driving one or more pins to a first value or a second value.
    Type: Application
    Filed: November 27, 2023
    Publication date: June 6, 2024
    Inventors: Martin Brox, Thomas Hein, Filippo Vitale
  • Publication number: 20240176695
    Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds may be configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device may configure a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device may track or count errors in the data and determine whether the threshold has been satisfied. The memory device may transmit (e.g., to the host device) an indication whether the threshold has been satisfied, and the system may perform functions to correct the errors and/or prevent further errors. The memory device may also identify errors in received commands or may identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Michael Dieter Richter, Thomas Hein, Wolfgang Anton Spirkl, Martin Brox, Peter Mayer
  • Patent number: 11989140
    Abstract: Methods, systems, and devices for signal path biasing in an electronic system (e.g., a memory system) are described. In one example, a memory device, a host device, or both may be configured to bias a signal path, between an idle state and an information transfer or between an information transfer and an idle state, to an intermediate or mid-bias voltage level, which may reduce signal interference associated with such transitions. In various examples, the described biasing to a voltage, such as a mid-bias voltage, may be associated with an access command or other command for information to be communicated between devices of the electronic system, such as a command for information to be communicated between a memory device and a host device.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Wolfgang Anton Spirkl, Thomas Hein, Martin Brox, Peter Mayer, Michael Dieter Richter
  • Publication number: 20240153542
    Abstract: Methods, systems, and devices for voltage overshoot mitigation at a device are described. The device may include a first driver circuit configured to generate data symbols on a transmission line and may include a second driver circuit configured to pre-emphasize the data symbols on the transmission line. The device may include a first inductor and a second inductor in series with the transmission line. A conductive line may couple the second driver circuit with a node, of the transmission line, that is between the first inductor and the second inductor.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Inventors: Martin Brox, Martin Bach, Thomas Hein
  • Publication number: 20240126644
    Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Martin Brox, Peter Mayer, Wolfgang Anton Spirkl, Thomas Hein, Michael Dieter Richter, Timothy M. Hollis, Roy Greeff
  • Patent number: 11948622
    Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Martin Brox, C. Omar Benitez, Johnathan L. Gossi, Christopher John Kawamura
  • Publication number: 20240095119
    Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.
    Type: Application
    Filed: June 19, 2023
    Publication date: March 21, 2024
    Inventors: Peter Mayer, Thomas Hein, Martin Brox, Wolfgang Anton Spirkl, Michael Dieter Richter
  • Patent number: 11914467
    Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds may be configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device may configure a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device may track or count errors in the data and determine whether the threshold has been satisfied. The memory device may transmit (e.g., to the host device) an indication whether the threshold has been satisfied, and the system may perform functions to correct the errors and/or prevent further errors. The memory device may also identify errors in received commands or may identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: February 27, 2024
    Inventors: Michael Dieter Richter, Thomas Hein, Wolfgang Anton Spirkl, Martin Brox, Peter Mayer
  • Publication number: 20240053908
    Abstract: Methods, systems, and devices for temperature-dependent refresh operations are described. A memory system may adjust refresh operations based on a temperature of the memory system to reduce a refresh current and improve reliability of the refresh operations. For example, the memory system may include a temperature sensor configured to provide temperature information associated with a memory device. Based on the temperature information, the memory system may, in response to a refresh command, activate a set of access lines (e.g., word lines) to refresh memory cells coupled with the access lines, where a count of the set of access lines (e.g., how many access lines are included in the set) may be based on the temperature information. In some examples, the count of the set may be determined based on comparing the temperature information to one or more temperature thresholds.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: Martin Brox, Elena Cabrera Bernal, Milena Tsevetkova Ivanov, Manfred Hans Plan, Oleg Sakolski, Filippo Vitale
  • Publication number: 20240028450
    Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.
    Type: Application
    Filed: June 23, 2023
    Publication date: January 25, 2024
    Inventors: Stefan Dietrich, Martin Brox, Michael Dieter Richter, Thomas Hein, Ronny Schneider, Natalija Jovanovic
  • Patent number: 11870616
    Abstract: Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Stefan Dietrich, Natalija Jovanovic, Ronny Schneider, Martin Brox, Thomas Hein, Michael Dieter Richter