Abstract: Methods, systems, and devices for voltage overshoot mitigation at a device are described. The device may include a first driver circuit configured to generate data symbols on a transmission line and may include a second driver circuit configured to pre-emphasize the data symbols on the transmission line. The device may include a first inductor and a second inductor in series with the transmission line. A conductive line may couple the second driver circuit with a node, of the transmission line, that is between the first inductor and the second inductor.

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.

Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds may be configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device may configure a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device may track or count errors in the data and determine whether the threshold has been satisfied. The memory device may transmit (e.g., to the host device) an indication whether the threshold has been satisfied, and the system may perform functions to correct the errors and/or prevent further errors. The memory device may also identify errors in received commands or may identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

Abstract: Methods, systems, and devices for temperature-dependent refresh operations are described. A memory system may adjust refresh operations based on a temperature of the memory system to reduce a refresh current and improve reliability of the refresh operations. For example, the memory system may include a temperature sensor configured to provide temperature information associated with a memory device. Based on the temperature information, the memory system may, in response to a refresh command, activate a set of access lines (e.g., word lines) to refresh memory cells coupled with the access lines, where a count of the set of access lines (e.g., how many access lines are included in the set) may be based on the temperature information. In some examples, the count of the set may be determined based on comparing the temperature information to one or more temperature thresholds.

Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Abstract: Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Abstract: Methods, systems, and devices for power-efficient access line operation for memory are described. A memory device may drive a voltage pulse on a first word line included in a set of word lines that is coupled with a master word line. The memory device may then a voltage pulse on a second word line included in the set of word lines coupled with the master word line. In between driving the voltage pulse on the first word line and driving the voltage pulse on the second word line, the memory device may maintain a voltage on the master word line below a threshold level.

Abstract: Methods, systems, and devices for tracking a reference voltage (also referred to as VREFD) after boot-up are described. For example, a host device or a memory device may determine a temperature value associated with the memory device. The host device or the memory device may select a reference voltage offset value for the memory device based on mapping the temperature value associated with the memory device to a relationship between reference voltage offset values and temperature differential values associated with the memory device. The host device or the memory device may adjust a reference voltage value associated with the memory device based on the reference voltage offset value. The host device, or the memory device, may operate the memory device in accordance with the reference voltage value based on adjusting the reference voltage value.

Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.

Abstract: Methods, systems, and devices for receive-side crosstalk cancelation are described. A device that receives multiple signals over different transmission lines may include a circuit for canceling crosstalk. The circuit may include one or more capacitors or inductors that are coupled with the inputs of multiple receive circuits. The circuit may also include a set of resistors that are coupled with the receive circuits. In some cases, the device may dynamically configure the cancelation circuit to provide a particular bandwidth or strength of cancelation. In such cases, the device may configure the circuit autonomously or based on control information from another device.

Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output are transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Abstract: Methods, systems, and devices for testing of multi-level signaling associated with a memory device are described. A tester may be used to test one or more operations of a memory device. The memory device may be configured to communicate data using a modulation scheme that includes three or more symbols. The tester may be configured to communicate data using a modulation scheme that includes three or fewer symbols. Techniques for testing the memory device using such a tester are described.

Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.