Abstract: Methods, systems, and devices for data alignment for memory are described. A memory device may implement individual time adjustments to align portions of a multilevel signal modulated by a modulation scheme with three levels. In some cases, signal paths for generating and transmitting the portions of the multilevel signal may reference a clock signal, and adjustable delay circuits may apply individual delays to the clock signal received at each signal path. For example, a first adjustable delay circuit may apply a first time adjustment to the clock signal received at a first signal path for generating a first portion. And, a second adjustable delay circuit may apply a second time adjustment to the clock signal received at a second signal path for generating a second portion. Applying the time adjustments to the signal paths may align the portions of the multilevel signal in time, compared to the clock signal.

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

Abstract: Methods, systems, and devices implementing self-timing read termination are described. A memory system may perform a read operation in which the memory system generates a first signal and a second signal to couple a first sense component and a second sense component with a global access line, respectively. The first sense component may be coupled with one or more memory cells via an access line, and the second sense component may be configured to determine one or more logic values of the one or more memory cells based on the coupling with the global access line. The memory system may support a self-timed termination of the first signal to decouple the first sense component from the global access line. The memory system may generate a third signal to terminate the first signal based on determining the one or more logic values.

Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Abstract: Methods, systems, and devices for temperature-based memory management are described. A system may include a memory device and a host device. The host device may identify a temperature (e.g., of the memory device). The host device may determine a value for a parameter for operating the memory device—such as a timing, voltage, or frequency parameter—based on the temperature of the memory device. The host device may transmit signaling to the memory device or another component of the system based on the value of the parameter. In some cases, the host device may determine the temperature of the memory device based on an indication (e.g., provided by the memory device). In some cases, the host device may determine the temperature of the memory device based on a temperature of the host device or a temperature of another component of the system.

Abstract: Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

Abstract: Methods, systems, and devices for power-efficient access line operation for memory are described. A memory device may drive a voltage pulse on a first word line included in a set of word lines that is coupled with a master word line. The memory device may then a voltage pulse on a second word line included in the set of word lines coupled with the master word line. In between driving the voltage pulse on the first word line and driving the voltage pulse on the second word line, the memory device may maintain a voltage on the master word line below a threshold level.

Abstract: Methods, systems, and devices for latency synchronization are described. A memory device may receive a data clock signal having a first rate and may generate a second clock signal having a second rate based on the data clock signal. A sampler may sample a first command signal indicating a command, where the second clock signal includes a first delay. A synchronizer may receive a second command signal from the sampler and a third clock signal from the sampler, where the second command signal and the third clock signal include a second delay. The synchronizer may synchronize a first timing of the second clock signal with a second timing of the third clock signal based on receiving the second command signal and the third clock signal and may output a signal including the second command signal and a synchronized clock signal having the second rate based on the synchronization.

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Abstract: Methods, systems, and devices for accessing multiple segments of memory systems are described. A memory device may be configured to concurrently activate two or more segments in a same row of a bank of memory cells based on determining whether the segments are concurrently accessible. For example, during a concurrent access operation on two memory cells in two segments of the same row, the memory device may determine whether the segments are concurrently inaccessible. If the segments are concurrently inaccessible, the memory device may discard a later access command or wait to perform the later access command until the corresponding segment is accessible. If the segments are concurrently accessible, the memory device may access both segments at least partially concurrently. The memory device may transmit an indication to a host device based on determining whether the concurrent access operation may be performed.

Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.

Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Abstract: Methods, systems, and devices for techniques and devices to reduce bus cross talk are described. Adjacent conductive lines in a bus of a memory system may be electrically coupled if both conductive lines are concurrently driven to a high-state. For example, the bus may include a logic circuit coupled between the adjacent conductive lines, which may selectively couple the conductive lines based on the voltage applied to each conductive line. In some examples, the logic circuit may include an input coupled to the control signals of the drivers associated with the adjacent conductive lines. If both control signals are concurrently high, the logic circuit may activate a transistor to couple the conductive lines. Such electrical coupling may reduce or eliminate the capacitive coupling between the two conductive lines when both are driven to a high state, which may result in increased reliability of signals in the conductive lines.

Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output is transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Abstract: Methods, systems, and devices for tracking a reference voltage (also referred to as VREFD) after boot-up are described. For example, a host device or a memory device may determine a temperature value associated with the memory device. The host device or the memory device may select a reference voltage offset value for the memory device based on mapping the temperature value associated with the memory device to a relationship between reference voltage offset values and temperature differential values associated with the memory device. The host device or the memory device may adjust a reference voltage value associated with the memory device based on the reference voltage offset value. The host device, or the memory device, may operate the memory device in accordance with the reference voltage value based on adjusting the reference voltage value.

Abstract: Methods, systems, and devices for operating memory cell(s) using adapting the current on a channel are described. A current on a channel may be adapted during a transition period between signaling a first logic value over the channel and signaling a second (e.g. subsequent) logic value over the channel. Adapting the current may include increasing or decreasing the current on the channel during the transition period. The degree of adaptation may be based on a difference between the first logic value and the subsequent logic value. In some cases, a logic circuit may be configured to determine a difference between the first and subsequent logic value. The logic circuit may be further configured to communicate the difference to an adaptive driver. And the adaptive driver may adapt a current of the channel based on the communicated difference.

Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.

Abstract: Methods, systems, and devices for temperature sensor linearization techniques are described. A temperature sensor associated with a semiconductor device may include a first circuit and a second circuit. The second circuit may be configured to determine that a first temperature, associated with the semiconductor device and indicated by one or more first bits generated by the first circuit, is within a first temperature range of a total temperature range measurable by the temperature sensor. The second circuit may be configured to generate and output, based on the first temperature being within the first temperature range, one or more second bits indicating a second temperature associated with the semiconductor device. The second circuit may generate the one or more second bits by applying, to the one or more first bits, a first-order operation corresponding to the first temperature range and associated with correcting an error of the first temperature.