Abstract: A method for identifying maximal independent sets in parallel may include, on a processor, accessing data representing an undirected graph, generating a respective initial priority value for each vertex, dependent on the vertex degree and an average degree for vertices in the graph, and recording an indication of the initial priority value for each vertex. The method may include determining, for multiple vertices, that no neighbor vertex has a priority value that is higher than that of the vertex. In response, the method may include recording respective indications that each neighbor vertex connected is not to be included in a maximal independent set for the undirected graph and recording an indication that the vertex is to be included in the maximal independent set. The determinations and recordings may be performed in parallel by respective processing elements of the processor. The processor may be a GPU.

Abstract: A method for identifying maximal independent sets in parallel may include, on a processor, accessing data representing an undirected graph, generating a respective initial priority value for each vertex, dependent on the vertex degree and an average degree for vertices in the graph, and recording an indication of the initial priority value for each vertex. The method may include determining, for multiple vertices, that no neighbor vertex has a priority value that is higher than that of the vertex. In response, the method may include recording respective indications that each neighbor vertex connected is not to be included in a maximal independent set for the undirected graph and recording an indication that the vertex is to be included in the maximal independent set. The determinations and recordings may be performed in parallel by respective processing elements of the processor. The processor may be a GPU.

Abstract: A method described herein includes at a computing device, receiving, over a network connection, a data packet from an external source, wherein the data packet comprises a compressed abstract syntax tree (AST)-based representation of source code written in a scripting language. The method further includes decompressing the compressed AST-based representation of the source code to generate a decompressed AST. The method also includes causing at least one processor on the computing device to execute at least one instruction represented in the decompressed AST subsequent to the compressed AST-based representation of the source code being decompressed.

Abstract: A prefetching technique referred to as future execution (FE) dynamically creates a prefetching thread for each active thread in a processor by simply sending a copy of all committed, register-writing instructions in a primary thread to an otherwise idle processor. On the way to the second processor, a value predictor replaces each predictable instruction with a load immediate instruction, where the immediate is the predicted result that the instruction is likely to produce during its nth next dynamic execution. Executing this modified instruction stream (i.e., the prefetching thread) in another processor allows computation of the future results of the instructions that are not directly predictable. This causes the issuance of prefetches into the shared memory hierarchy, thereby reducing the primary thread's memory access time and speeding up the primary thread's execution.

Abstract: A prefetching technique referred to as future execution (FE) dynamically creates a prefetching thread for each active thread in a processor by simply sending a copy of all committed, register-writing instructions in a primary thread to an otherwise idle processor. On the way to the second processor, a value predictor replaces each predictable instruction with a load immediate instruction, where the immediate is the predicted result that the instruction is likely to produce during its nth next dynamic execution. Executing this modified instruction stream (i.e., the prefetching thread) in another processor allows computation of the future results of the instructions that are not directly predictable. This causes the issuance of prefetches into the shared memory hierarchy, thereby reducing the primary thread's memory access time and speeding up the primary thread's execution.